公开(公告)号：US08551876B2

公开(公告)日：2013-10-08

申请号：US13212187

申请日：2011-08-18

Applicant: Yu-Ren Wang ,  Te-Lin Sun ,  Szu-Hao Lai ,  Po-Chun Chen ,  Chih-Hsun Lin ,  Che-Nan Tsai ,  Chun-Ling Lin ,  Chiu-Hsien Yeh

Inventor： Yu-Ren Wang ,  Te-Lin Sun ,  Szu-Hao Lai ,  Po-Chun Chen ,  Chih-Hsun Lin ,  Che-Nan Tsai ,  Chun-Ling Lin ,  Chiu-Hsien Yeh

IPC: H01L21/28

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7848

Abstract: A manufacturing method for a semiconductor device having a metal gate includes providing a substrate having at least a first semiconductor device formed thereon, forming a first gate trench in the first semiconductor device, forming a first work function metal layer in the first gate trench, and performing a decoupled plasma oxidation to the first work function metal layer.

Abstract translation: 具有金属栅极的半导体器件的制造方法包括提供至少形成有第一半导体器件的衬底，在第一半导体器件中形成第一栅极沟槽，在第一栅极沟槽中形成第一功函数金属层，以及 对第一功函数金属层进行解耦等离子体氧化。

公开(公告)号：US09000568B2

公开(公告)日：2015-04-07

申请号：US13244948

申请日：2011-09-26

Applicant: Szu-Hao Lai ,  Yu-Ren Wang ,  Po-Chun Chen ,  Chih-Hsun Lin ,  Che-Nan Tsai ,  Chun-Ling Lin ,  Chiu-Hsien Yeh ,  Te-Lin Sun

Inventor： Szu-Hao Lai ,  Yu-Ren Wang ,  Po-Chun Chen ,  Chih-Hsun Lin ,  Che-Nan Tsai ,  Chun-Ling Lin ,  Chiu-Hsien Yeh ,  Te-Lin Sun

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure.

Abstract translation: 半导体结构包括基板，氧化物层，金属氧氮化物层和金属氧化物层。 氧化物层位于衬底上。 金属氮氧化物层位于氧化物层上。 金属氧化物层位于金属氮氧化物层上。 此外，本发明还提供了一种用于形成半导体结构的半导体工艺。

公开(公告)号：US20140057434A1

公开(公告)日：2014-02-27

申请号：US13593517

申请日：2012-08-24

Applicant: Jia-Jia Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Ching-Wei Hsu ,  Szu-Hao Lai ,  Huei-Ru Tsai ,  Tsai-Yu Wen ,  Ching-Li Yang ,  Chien-Li Kuo

Inventor： Jia-Jia Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Ching-Wei Hsu ,  Szu-Hao Lai ,  Huei-Ru Tsai ,  Tsai-Yu Wen ,  Ching-Li Yang ,  Chien-Li Kuo

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through silicon via process includes the following steps. A substrate having a front side and a back side is provided. A passivation layer is formed on the back side of the substrate. An oxide layer is formed on the passivation layer.

Abstract translation: 硅通孔工艺包括以下步骤。 提供具有正面和背面的基板。 在基板的背面形成钝化层。 在钝化层上形成氧化物层。

公开(公告)号：US20130075874A1

公开(公告)日：2013-03-28

申请号：US13244948

申请日：2011-09-26

Applicant: Szu-Hao Lai ,  Yu-Ren Wang ,  Po-Chun Chen ,  Chih-Hsun Lin ,  Che-Nan Tsai ,  Chun-Ling Lin ,  Chiu-Hsien Yeh ,  Te-Lin Sun

Inventor： Szu-Hao Lai ,  Yu-Ren Wang ,  Po-Chun Chen ,  Chih-Hsun Lin ,  Che-Nan Tsai ,  Chun-Ling Lin ,  Chiu-Hsien Yeh ,  Te-Lin Sun

IPC: H01L29/06 ,  H01L21/31

CPC classification number: H01L21/28185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure.

Abstract translation: 半导体结构包括基板，氧化物层，金属氧氮化物层和金属氧化物层。 氧化物层位于衬底上。 金属氮氧化物层位于氧化物层上。 金属氧化物层位于金属氮氧化物层上。 此外，本发明还提供了一种用于形成半导体结构的半导体工艺。

公开(公告)号：US09012324B2

公开(公告)日：2015-04-21

申请号：US13593517

申请日：2012-08-24

Applicant: Jia-Jia Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Ching-Wei Hsu ,  Szu-Hao Lai ,  Huei-Ru Tsai ,  Tsai-Yu Wen ,  Ching-Li Yang ,  Chien-Li Kuo

Inventor： Jia-Jia Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Ching-Wei Hsu ,  Szu-Hao Lai ,  Huei-Ru Tsai ,  Tsai-Yu Wen ,  Ching-Li Yang ,  Chien-Li Kuo

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through silicon via process includes the following steps. A substrate having a front side and a back side is provided. A passivation layer is formed on the back side of the substrate. An oxide layer is formed on the passivation layer.

Abstract translation: 硅通孔工艺包括以下步骤。 提供具有正面和背面的基板。 在基板的背面形成钝化层。 在钝化层上形成氧化物层。

公开(公告)号：US20130012012A1

公开(公告)日：2013-01-10

申请号：US13179558

申请日：2011-07-10

Applicant: Chien-Liang Lin ,  Yu-Ren Wang ,  Ying-Wei Yen ,  Shao-Wei Wang ,  Te-Lin Sun ,  Szu-Hao Lai ,  Po-Chun Chen ,  Chih-Hsun Lin ,  Che-Nan Tsai ,  Chun-Ling Lin ,  Chiu-Hsien Yeh

Inventor： Chien-Liang Lin ,  Yu-Ren Wang ,  Ying-Wei Yen ,  Shao-Wei Wang ,  Te-Lin Sun ,  Szu-Hao Lai ,  Po-Chun Chen ,  Chih-Hsun Lin ,  Che-Nan Tsai ,  Chun-Ling Lin ,  Chiu-Hsien Yeh

IPC: H01L21/28

CPC classification number: H01L21/268 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/51

Abstract: A semiconductor process includes the following steps. A substrate having an oxide layer thereon is provided. A high temperature process higher than 1000° C. is performed to form a melting layer between the substrate and the oxide layer. A removing process is performed to remove the oxide layer and the melting layer.

Abstract translation: 半导体工艺包括以下步骤。 提供其上具有氧化物层的衬底。 进行高于1000℃的高温处理，以在基板和氧化物层之间形成熔融层。 进行去除处理以去除氧化物层和熔化层。

公开(公告)号：US20120306028A1

公开(公告)日：2012-12-06

申请号：US13118561

申请日：2011-05-30

Applicant: Yu-Ren Wang ,  Te-Lin Sun ,  Szu-Hao Lai ,  Po-Chun Chen ,  Chih-Hsun Lin ,  Che-Nan Tsai ,  Chun-Ling Lin ,  Chiu-Hsien Yeh ,  Chien-Liang Lin ,  Shao-Wei Wang ,  Ying-Wei Yen

Inventor： Yu-Ren Wang ,  Te-Lin Sun ,  Szu-Hao Lai ,  Po-Chun Chen ,  Chih-Hsun Lin ,  Che-Nan Tsai ,  Chun-Ling Lin ,  Chiu-Hsien Yeh ,  Chien-Liang Lin ,  Shao-Wei Wang ,  Ying-Wei Yen

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L21/28202 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: A semiconductor process is provided, including: a substrate is provided, a buffer layer is formed, and a dielectric layer having a high dielectric constant is formed, wherein the methods of forming the buffer layer include: (1) an oxidation process is performed; and a baking process is performed; Alternatively, (2) an oxidation process is performed; a thermal nitridation process is performed; and a plasma nitridation process is performed; Or, (3) a decoupled plasma oxidation process is performed. Furthermore, a semiconductor structure fabricated by the last process is also provided.

Abstract translation: 提供一种半导体工艺，包括：提供衬底，形成缓冲层，形成介电常数高的介电层，其中形成缓冲层的方法包括：（1）进行氧化处理; 进行烘烤处理; 或者，（2）进行氧化处理; 进行热氮化处理; 并进行等离子体氮化处理; 或者，（3）进行去耦等离子体氧化处理。 此外，还提供了通过最后工艺制造的半导体结构。

公开(公告)号：US20130045594A1

公开(公告)日：2013-02-21

申请号：US13212187

申请日：2011-08-18

Applicant: Yu-Ren Wang ,  Te-Lin Sun ,  Szu-Hao Lai ,  Po-Chun Chen ,  Chih-Hsun Lin ,  Che-Nan Tsai ,  Chun-Ling Lin ,  Chiu-Hsien Yeh

Inventor： Yu-Ren Wang ,  Te-Lin Sun ,  Szu-Hao Lai ,  Po-Chun Chen ,  Chih-Hsun Lin ,  Che-Nan Tsai ,  Chun-Ling Lin ,  Chiu-Hsien Yeh

IPC: H01L21/28

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7848

Abstract: A manufacturing method for a semiconductor device having a metal gate includes providing a substrate having at least a first semiconductor device formed thereon, forming a first gate trench in the first semiconductor device, forming a first work function metal layer in the first gate trench, and performing a decoupled plasma oxidation to the first work function metal layer.

Abstract translation: 具有金属栅极的半导体器件的制造方法包括提供至少形成有第一半导体器件的衬底，在第一半导体器件中形成第一栅极沟槽，在第一栅极沟槽中形成第一功函数金属层，以及 对第一功函数金属层进行解耦等离子体氧化。

公开(公告)号：US20120071004A1

公开(公告)日：2012-03-22

申请号：US12885110

申请日：2010-09-17

Applicant: Jei-Ming CHEN ,  Szu-Hao LAI

Inventor： Jei-Ming CHEN ,  Szu-Hao LAI

IPC: H01L21/31

CPC classification number: H01L21/26506 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7847

Abstract: A stress-adjusting method for use in a manufacturing system of a MOS device is provided. At first, a first stress layer is formed onto a substrate wherein at least two MOSFETs are previously formed on the substrate. The first stress layer overlies an inter-gate region between two adjacent gate regions of the MOSFETs and overlies the two adjacent gate regions. Then, the first stress layer in the inter-gate region is thinned. A second stress layer is further formed onto the substrate to overlie the thinned first stress layer in the inter-gate region to provide the resulting MOS device with satisfactory stress.

Abstract translation: 提供了一种用于MOS器件制造系统的应力调节方法。 首先，在衬底上形成第一应力层，其中在衬底上预先形成至少两个MOSFET。 第一应力层覆盖在MOSFET的两个相邻栅极区域之间的栅极间区域，并且覆盖在两个相邻栅极区域上。 然后，栅极间区域中的第一应力层变薄。 第二应力层进一步形成在衬底上以覆盖栅极间区域中的减薄的第一应力层，以使所得到的MOS器件具有令人满意的应力。