公开(公告)号：US20130137243A1

公开(公告)日：2013-05-30

申请号：US13308513

申请日：2011-11-30

Applicant: Chan-Lon Yang ,  Ching-I Li ,  Ger-Pin Lin ,  I-Ming Lai ,  Yun-San Huang ,  Chin-I Liao ,  Chin-Cheng Chien

Inventor： Chan-Lon Yang ,  Ching-I Li ,  Ger-Pin Lin ,  I-Ming Lai ,  Yun-San Huang ,  Chin-I Liao ,  Chin-Cheng Chien

IPC: H01L21/20

CPC classification number: H01L29/6656 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

Abstract: First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below −30° C.

Abstract translation: 首先，在半导体工艺中设置具有凹部的基板。 第二，在衬底中形成嵌入的SiGe层。 嵌入的SiGe层包括填充凹槽的外延SiGe材料。 然后，在嵌入的SiGe层上进行预非晶化植入（PAI）工艺以形成非晶区域。 接下来，在嵌入的SiGe层上进行源极/漏极注入工艺以形成源极掺杂区域和漏极掺杂区域。 之后，进行源极/漏极退火处理以在衬底中形成源极和漏极。 前非晶化植入程序和源极/漏极注入程序中的至少一个在低于-30℃的低温过程中进行。

公开(公告)号：US08536072B2

公开(公告)日：2013-09-17

申请号：US13368006

申请日：2012-02-07

Applicant: Chan-Lon Yang ,  Ching-Nan Hwang ,  Chi-Heng Lin ,  Chun-Yao Yang ,  Ger-Pin Lin ,  Ching-I Li

Inventor： Chan-Lon Yang ,  Ching-Nan Hwang ,  Chi-Heng Lin ,  Chun-Yao Yang ,  Ger-Pin Lin ,  Ching-I Li

IPC: H01L21/00

CPC classification number: H01L28/24 ,  H01L21/26593 ,  H01L21/32155 ,  H01L21/76224 ,  H01L27/0629 ,  H01L28/20

Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.

Abstract translation: 提供半导体工艺，包括以下步骤。 在基板上形成多晶硅层。 对多晶硅层进行不对称双面加热处理，其中用于正面加热的功率不同于用于背面加热的功率。

公开(公告)号：US20110177665A1

公开(公告)日：2011-07-21

申请号：US12691723

申请日：2010-01-21

Applicant: Chan-Lon Yang ,  Ching-I Li ,  Tzu-Feng Kuo

Inventor： Chan-Lon Yang ,  Ching-I Li ,  Tzu-Feng Kuo

IPC: H01L21/336 ,  H01L21/26

CPC classification number: H01L21/268 ,  H01L29/6659 ,  H01L29/7833

Abstract: A thermal process is disclosed. The thermal process preferably includes the steps of: providing a semiconductor substrate ready to be heated; and utilizing at least a first heating beam and a second heating beam with different energy density to heat the semiconductor substrate simultaneously. Accordingly, the present invention no only eliminates the need of switching between two different thermal processing equipments and shortens the overall fabrication cycle time, but also improves the pattern effect caused by the conventional front side heating.

Abstract translation: 公开了一种热处理。 热处理优选包括以下步骤：提供准备加热的半导体衬底; 并且利用至少第一加热束和具有不同能量密度的第二加热束同时加热半导体衬底。 因此，本发明不仅消除了在两个不同的热处理设备之间切换的需要，并且缩短了整个制造周期时间，而且还改善了由常规的前侧加热引起的图案效应。

公开(公告)号：US20080210667A1

公开(公告)日：2008-09-04

申请号：US11681745

申请日：2007-03-02

Applicant: Chan-lon Yang ,  Ching-I Li

Inventor： Chan-lon Yang ,  Ching-I Li

IPC: B23K26/00

CPC classification number: B23K26/03 ,  H01L21/268

Abstract: A rapid thermal process method contains providing a substrate, performing a pre-heating process to at least a first portion of the substrate by means of a first laser beam, and performing a rapid heating process to the pre-heated first portion of the substrate by means of a second laser beam.

Abstract translation: 快速热处理方法包括提供基板，通过第一激光束对基板的至少第一部分进行预热处理，并且通过以下步骤对基板的预加热的第一部分进行快速加热处理： 第二激光束的装置。

公开(公告)号：US08921206B2

公开(公告)日：2014-12-30

申请号：US13308513

申请日：2011-11-30

Applicant: Chan-Lon Yang ,  Ching-I Li ,  Ger-Pin Lin ,  I-Ming Lai ,  Yun-San Huang ,  Chin-I Liao ,  Chin-Cheng Chien

Inventor： Chan-Lon Yang ,  Ching-I Li ,  Ger-Pin Lin ,  I-Ming Lai ,  Yun-San Huang ,  Chin-I Liao ,  Chin-Cheng Chien

IPC: H01L21/36

CPC classification number: H01L29/6656 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

Abstract: First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below −30° C.

Abstract translation: 首先，在半导体工艺中设置具有凹部的基板。 第二，在衬底中形成嵌入的SiGe层。 嵌入的SiGe层包括填充凹槽的外延SiGe材料。 然后，在嵌入的SiGe层上进行预非晶化植入（PAI）工艺以形成非晶区域。 接下来，在嵌入的SiGe层上进行源极/漏极注入工艺以形成源极掺杂区域和漏极掺杂区域。 之后，进行源极/漏极退火处理以在衬底中形成源极和漏极。 前非晶化植入程序和源极/漏极注入程序中的至少一个在低于-30℃的低温过程中进行。

公开(公告)号：US08575043B2

公开(公告)日：2013-11-05

申请号：US13191430

申请日：2011-07-26

Applicant: Chan-Lon Yang ,  Tzu-Feng Kuo ,  Hsin-Huei Wu ,  Ching-I Li ,  Shu-Yen Chan

Inventor： Chan-Lon Yang ,  Tzu-Feng Kuo ,  Hsin-Huei Wu ,  Ching-I Li ,  Shu-Yen Chan

IPC: H01L21/00 ,  B23K26/02 ,  B23K26/08

CPC classification number: H01L21/268 ,  H01L21/26586

Abstract: A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an included angle.

Abstract translation: 半导体器件包括设置在半导体衬底上的多个有源区。 半导体器件的制造方法包括：通过在第一扫描方向上单独地发射第一激光，对半导体衬底进行第一退火处理，并且通过在第二扫描方向上单独地发射第二激光，对半导体衬底进行第二退火处理。 第一扫描方向和第二扫描方向具有夹角。

公开(公告)号：US20130203226A1

公开(公告)日：2013-08-08

申请号：US13368006

申请日：2012-02-07

Applicant: Chan-Lon Yang ,  Ching-Nan Hwang ,  Chi-Heng Lin ,  Chun-Yao Yang ,  Ger-Pin Lin ,  Ching-I Li

Inventor： Chan-Lon Yang ,  Ching-Nan Hwang ,  Chi-Heng Lin ,  Chun-Yao Yang ,  Ger-Pin Lin ,  Ching-I Li

IPC: H01L21/283 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L28/24 ,  H01L21/26593 ,  H01L21/32155 ,  H01L21/76224 ,  H01L27/0629 ,  H01L28/20

Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a forntside heating is different from a power for a backside heating.

Abstract translation: 提供半导体工艺，包括以下步骤。 在基板上形成多晶硅层。 对多晶硅层进行不对称双面加热处理，其中用于正面加热的功率不同于用于背面加热的功率。

公开(公告)号：US20130026543A1

公开(公告)日：2013-01-31

申请号：US13191430

申请日：2011-07-26

Applicant: Chan-Lon Yang ,  Tzu-Feng Kuo ,  Hsin-Huei Wu ,  Ching-I Li ,  Shu-Yen Chan

Inventor： Chan-Lon Yang ,  Tzu-Feng Kuo ,  Hsin-Huei Wu ,  Ching-I Li ,  Shu-Yen Chan

IPC: H01L21/268 ,  H01L29/772

CPC classification number: H01L21/268 ,  H01L21/26586

Abstract: A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an incident angle.

Abstract translation: 半导体器件包括设置在半导体衬底上的多个有源区。 半导体器件的制造方法包括：通过在第一扫描方向上单独地发射第一激光，对半导体衬底进行第一退火处理，并且通过在第二扫描方向上单独地发射第二激光，对半导体衬底进行第二退火处理。 第一扫描方向和第二扫描方向具有入射角。

公开(公告)号：US20100255666A1

公开(公告)日：2010-10-07

申请号：US12819337

申请日：2010-06-21

Applicant: Chan-Lon YANG ,  Ching-I Li ,  Tzu-Feng Kuo ,  Yin-Ru Shi

Inventor： Chan-Lon YANG ,  Ching-I Li ,  Tzu-Feng Kuo ,  Yin-Ru Shi

IPC: H01L21/265

CPC classification number: H01L21/76897 ,  H01L21/76801 ,  H01L21/76804 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thermal processing method is provided. First, a semiconductor substrate is provided. The semiconductor substrate has a metal-oxide-semiconductor transistor formed thereon. The metal-oxide-semiconductor transistor includes a gate and source and drain regions on two sides of the gate. Dopants are implanted into the source and drain region and the gate. Next, a cap layer is formed over the semiconductor substrate. Next, a first thermal process is performed, and then a second thermal process is performed. Next, the cap layer is removed. The thermal processing method is capable of uniformly heating a semiconductor substrate and reducing the pattern effect in the fabrication of a CMOS and to improve the performance of the CMOS.

Abstract translation: 提供了一种热处理方法。 首先，提供半导体基板。 半导体衬底具有形成在其上的金属氧化物半导体晶体管。 金属氧化物半导体晶体管包括在栅极两侧的栅极和源极和漏极区域。 掺杂剂注入到源极和漏极区域和栅极中。 接下来，在半导体衬底上形成覆盖层。 接下来，执行第一热处理，然后执行第二热处理。 接下来，去除盖层。 热处理方法能够均匀地加热半导体衬底并降低CMOS的制造中的图案效应并提高CMOS的性能。

公开(公告)号：US08486790B2

公开(公告)日：2013-07-16

申请号：US13184572

申请日：2011-07-18

Applicant: Po-Cheng Huang ,  Kuo-Chih Lai ,  Ching-I Li ,  Yu-Shu Lin ,  Ya-Jyuan Hung ,  Yen-Liang Lu ,  Yu-Wen Wang ,  Hsin-Chih Yu

Inventor： Po-Cheng Huang ,  Kuo-Chih Lai ,  Ching-I Li ,  Yu-Shu Lin ,  Ya-Jyuan Hung ,  Yen-Liang Lu ,  Yu-Wen Wang ,  Hsin-Chih Yu

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/7833

Abstract: A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.

Abstract translation: 金属栅极的制造方法包括提供具有形成在其上的电介质层和多晶硅层的基板，多晶硅层，在多晶硅层上形成保护层，在保护层上形成图案化的硬掩模，进行第一蚀刻工艺 蚀刻保护层和多晶硅层，以在衬底上形成具有第一高度的虚拟栅极，形成覆盖图案化硬掩模和伪栅极的多层介电结构，去除伪栅极以在衬底上形成栅极沟槽， 以及在所述栅极沟槽中形成具有第二高度的金属栅极。 金属栅极的第二高度基本上等于虚拟栅极的第一高度。