公开(公告)号：US20100255666A1

公开(公告)日：2010-10-07

申请号：US12819337

申请日：2010-06-21

Applicant: Chan-Lon YANG ,  Ching-I Li ,  Tzu-Feng Kuo ,  Yin-Ru Shi

Inventor： Chan-Lon YANG ,  Ching-I Li ,  Tzu-Feng Kuo ,  Yin-Ru Shi

IPC: H01L21/265

CPC classification number: H01L21/76897 ,  H01L21/76801 ,  H01L21/76804 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thermal processing method is provided. First, a semiconductor substrate is provided. The semiconductor substrate has a metal-oxide-semiconductor transistor formed thereon. The metal-oxide-semiconductor transistor includes a gate and source and drain regions on two sides of the gate. Dopants are implanted into the source and drain region and the gate. Next, a cap layer is formed over the semiconductor substrate. Next, a first thermal process is performed, and then a second thermal process is performed. Next, the cap layer is removed. The thermal processing method is capable of uniformly heating a semiconductor substrate and reducing the pattern effect in the fabrication of a CMOS and to improve the performance of the CMOS.

Abstract translation: 提供了一种热处理方法。 首先，提供半导体基板。 半导体衬底具有形成在其上的金属氧化物半导体晶体管。 金属氧化物半导体晶体管包括在栅极两侧的栅极和源极和漏极区域。 掺杂剂注入到源极和漏极区域和栅极中。 接下来，在半导体衬底上形成覆盖层。 接下来，执行第一热处理，然后执行第二热处理。 接下来，去除盖层。 热处理方法能够均匀地加热半导体衬底并降低CMOS的制造中的图案效应并提高CMOS的性能。

公开(公告)号：US20130023103A1

公开(公告)日：2013-01-24

申请号：US13185567

申请日：2011-07-19

Applicant: Chan-Lon YANG ,  Ching-I LI ,  Ger-Pin LIN

Inventor： Chan-Lon YANG ,  Ching-I LI ,  Ger-Pin LIN

IPC: H01L21/336

CPC classification number: H01L29/7847 ,  H01L21/26593 ,  H01L29/7843

Abstract: A method for fabricating a semiconductor device is implemented by using a stress memorization technique. The method includes the following steps. Firstly, a substrate is provided, wherein a gate structure is formed over the substrate. Then, a pre-amorphization implantation process is performed to define an amorphized region at a preset area of the substrate with the gate structure serving as an implantation mask. During the pre-amorphization implantation process is performed, the substrate is controlled at a temperature lower than room temperature. Then, a stress layer is formed on the gate structure and a surface of the amorphized region. Then, a thermal treatment process is performed to re-crystallize the amorphized region of the substrate. Afterwards, the stress layer is removed.

Abstract translation: 通过使用应力记忆技术来实现半导体器件的制造方法。 该方法包括以下步骤。 首先，提供衬底，其中在衬底上形成栅极结构。 然后，执行预非晶化注入工艺以在栅极结构用作注入掩模的衬底的预设区域处限定非晶化区域。 在非晶化期间，进行注入工艺，将衬底控制在低于室温的温度。 然后，在栅极结构和非晶化区域的表面上形成应力层。 然后，进行热处理工艺以重新结晶衬底的非晶化区域。 之后，去除应力层。

公开(公告)号：US20120238065A1

公开(公告)日：2012-09-20

申请号：US13482044

申请日：2012-05-29

Applicant: Chiu-Hsien YEH ,  Chan-Lon YANG ,  Chin-Cheng CHIEN ,  Lien-Fa HUNG ,  Yun-Cheng KAO

Inventor： Chiu-Hsien YEH ,  Chan-Lon YANG ,  Chin-Cheng CHIEN ,  Lien-Fa HUNG ,  Yun-Cheng KAO

IPC: H01L21/8238

CPC classification number: H01L29/517 ,  H01L21/31111 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/4966 ,  H01L29/513

Abstract: A method of fabricating a MOS device comprises steps as follows: An interfacial layer, a high-k dielectric layer and a cover layer on a substrate are sequentially formed. Then an in-situ wet etching step is performed by sequentially using a first etching solution to etch the cover layer and using a second etching solution to etch the high-k dielectric layer and the interfacial layer until the substrate is exposed, wherein the second etching solution is a mixed etching solution containing the first etching solution.

Abstract translation: 制造MOS器件的方法包括以下步骤：依次形成界面层，高k电介质层和衬底上的覆盖层。 然后，通过依次使用第一蚀刻溶液蚀刻覆盖层并使用第二蚀刻溶液来蚀刻高k电介质层和界面层直到基板被暴露来进行原位湿蚀刻步骤，其中第二蚀刻 溶液是含有第一蚀刻溶液的混合蚀刻溶液。

公开(公告)号：US20120058634A1

公开(公告)日：2012-03-08

申请号：US12874332

申请日：2010-09-02

Applicant: Chiu-Hsien YEH ,  Chan-Lon YANG ,  Chin-Cheng CHIEN ,  Lien-Fa HUNG ,  Yun-Cheng KAO

Inventor： Chiu-Hsien YEH ,  Chan-Lon YANG ,  Chin-Cheng CHIEN ,  Lien-Fa HUNG ,  Yun-Cheng KAO

IPC: H01L21/28

CPC classification number: H01L29/517 ,  H01L21/31111 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/4966 ,  H01L29/513

Abstract: A method of fabricating a CMOS device having high-k dielectric layer and metal gate electrode is provided. First, an isolation structure is formed in a substrate to define a first-type and a second-type MOS regions; an interfacial layer and a high-k dielectric layer are sequentially formed over the substrate; a first and a second cover layers are respectively formed over a portion of the high-k dielectric layer at the first-type MOS region and another portion of the high-k dielectric layer at the second-type MOS region; afterwards, an in-situ etching step is performed to sequentially etch the first and second cover layers using a first etching solution and to etch both the high-k dielectric layer and the interfacial layer using a second etching solution until the substrate is exposed. Wherein, the second etching solution is a mixed etching solution containing the first etching solution.

Abstract translation: 提供一种制造具有高k电介质层和金属栅电极的CMOS器件的方法。 首先，在衬底中形成隔离结构以限定第一类型和第二类型的MOS区; 在衬底上顺序地形成界面层和高k电介质层; 第一和第二覆盖层分别形成在第一型MOS区的高k电介质层的一部分和第二型MOS区的高k电介质层的另一部分上; 之后，执行原位蚀刻步骤以使用第一蚀刻溶液顺次蚀刻第一和第二覆盖层，并且使用第二蚀刻溶液蚀刻高k电介质层和界面层，直到基板被暴露。 其中，第二蚀刻溶液是含有第一蚀刻溶液的混合蚀刻溶液。

公开(公告)号：US20120003835A1

公开(公告)日：2012-01-05

申请号：US12830370

申请日：2010-07-05

Applicant: Chan-Lon YANG ,  Yeng-Peng Wang ,  Chiu-Hsien Yeh

Inventor： Chan-Lon YANG ,  Yeng-Peng Wang ,  Chiu-Hsien Yeh

IPC: H01L21/308 ,  H01L21/306

CPC classification number: H01L21/823842 ,  H01L21/32134 ,  H01L21/32135 ,  H01L27/11 ,  H01L27/1104

Abstract: An exemplary method of etching sacrificial layer includes steps of: providing a substrate formed with a sacrificial layer and defined with a first region and a second region, the sacrificial layer disposed in both the first and second regions; forming a hard mask covering the first region while exposing the second region; performing a first etching process on the sacrificial layer to thin the sacrificial layer while forming a byproduct film overlying the thinned sacrificial layer; performing a second etching process on the byproduct film to remove a portion of the byproduct layer for exposing a portion of the thinned sacrificial layer, while another portion of the byproduct film disposed on sidewalls of the thinned sacrificial layer being remained; and performing a third etching process on the thinned sacrificial layer, to remove the portion of the thinned sacrificial layer exposed in the second etching process.

Abstract translation: 蚀刻牺牲层的示例性方法包括以下步骤：提供形成有牺牲层并且由第一区域和第二区域限定的衬底，所述牺牲层设置在第一和第二区域中; 在暴露所述第二区域的同时形成覆盖所述第一区域的硬掩模; 在所述牺牲层上执行第一蚀刻工艺以使所述牺牲层变薄，同时形成覆盖所述薄化的牺牲层的副产物膜; 在副产品膜上执行第二蚀刻工艺以去除副产物层的一部分，用于暴露部分减薄的牺牲层，同时保留设置在减薄的牺牲层的侧壁上的副产物膜的另一部分; 以及对所述减薄的牺牲层执行第三蚀刻工艺，以去除在所述第二蚀刻工艺中暴露的所述薄化牺牲层的所述部分。

公开(公告)号：US20100264550A1

公开(公告)日：2010-10-21

申请号：US12825515

申请日：2010-06-29

Applicant: Chan-Lon YANG

Inventor： Chan-Lon YANG

IPC: H01L23/48

CPC classification number: H01L21/76897 ,  H01L21/76801 ,  H01L21/76804 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A self-aligned contact includes a lower contact disposed in a dielectric layer of a substrate and an upper contact disposed in the dielectric layer and directly on the lower contact, and electrically connected to the lower contact. The profile of the upper contact and the lower contact is zigzag.

Abstract translation: 自对准触点包括设置在基板的电介质层中的下触点和设置在电介质层中并直接在下触点上的上接触件，并且电连接到下触点。 上触点和下触点的外形为锯齿形。