公开(公告)号：US12237340B2

公开(公告)日：2025-02-25

申请号：US18026508

申请日：2022-06-23

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lizhong Wang ,  Jin Yang ,  Tianmin Zhou ,  Hui Guo

IPC: G02F1/1335 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/12

Abstract: The present disclosure provides a display substrate, a display panel and a display apparatus. The display substrate includes a base substrate; a transistor, located on the base substrate, and including an active layer; and a data line, located between the active layer and the base substrate; the data line is connected with the active layer, and an orthographic projection of the active layer on the base substrate is located in an orthographic projection of the data line on the base substrate.

公开(公告)号：US20190096920A1

公开(公告)日：2019-03-28

申请号：US16134201

申请日：2018-09-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Tianmin Zhou ,  Wei Yang ,  Lizhong Wang ,  Jipeng Song

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L21/3003 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/1251 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1296 ,  H01L29/78609 ,  H01L29/78675 ,  H01L29/7869

Abstract: an array substrate, a method of manufacturing the array substrate, and a display device are provided. The array substrate includes: a base substrate; a first thin film transistor and a second thin film transistor on the base substrate, wherein the first thin film transistor comprises a first active layer, the second thin film transistor comprises a second active layer, and the second active layer is on a side of the first active layer away from the base substrate; and an interlayer dielectric layer and a first buffer layer between the first active layer and the second active layer, wherein the interlayer dielectric layer is capable of supplying hydrogen and the first buffer layer is capable of blocking hydrogen.

公开(公告)号：US20220344517A1

公开(公告)日：2022-10-27

申请号：US17763297

申请日：2021-04-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jie Huang ,  Zhengliang Li ,  Ce Ning ,  Hehe Hu ,  Nianqi Yao ,  Kun Zhao ,  Fengjuan Liu ,  Tianmin Zhou ,  Liping Lei

IPC: H01L29/786

Abstract: A thin film transistor includes a gate electrode, an active layer, a gate insulating layer located between the gate electrode and the active layer, and a source electrode and a drain electrode electrically connected to the active layer. The active layer includes a channel layer and at least one channel protection layer; a material of each of the channel layer and the at least one channel protection layer is a metal oxide semiconductor material. The at least one channel protection layer is a crystallizing layer, and metal elements of the at least one channel protection layer include non-rare earth metal elements including In, Ga, Zn and Sn.

公开(公告)号：US11362114B2

公开(公告)日：2022-06-14

申请号：US16765216

申请日：2019-12-06

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wei Yang ,  Guangcai Yuan ,  Ce Ning ,  Xinhong Lu ,  Tianmin Zhou ,  Xin Yang

IPC: H01L27/12

Abstract: A method of manufacturing an array substrate includes: forming a first semiconductor pattern and a first insulating layer group sequentially on a base substrate; forming a second semiconductor pattern and a second insulating layer group sequentially on the first insulating layer group; forming two first via holes in the first insulating layer group and the second insulating layer group to expose the first semiconductor pattern, annealing the exposed first semiconductor pattern and then removing an oxide layer on a surface of the first semiconductor pattern; forming connecting wires in the first via holes; forming second via holes in the second insulating layer group to expose the second semiconductor pattern, and forming a first source electrode and a first drain electrode in the second via holes such that the first source electrode or the first drain electrode covers and is connected to one of the connecting wires.

公开(公告)号：US11239263B2

公开(公告)日：2022-02-01

申请号：US16074283

申请日：2018-01-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Tianmin Zhou ,  Wei Yang ,  Lizhong Wang ,  Xiaming Zhu ,  Jipeng Song

IPC: H01L27/12 ,  H01L29/786 ,  H01L33/44

Abstract: A thin film transistor, a method for manufacturing the same and a display device are disclosed. The thin film transistor includes source-drain electrodes and a passivation layer; an isolation layer is disposed between the source-drain electrodes and the passivation layer, and the isolation layer overlays the source-drain electrodes.

公开(公告)号：US12235557B2

公开(公告)日：2025-02-25

申请号：US17765769

申请日：2021-06-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhen Zhang ,  Fuqiang Li ,  Zhenyu Zhang ,  Yunping Di ,  Lizhong Wang ,  Zheng Fang ,  Jiahui Han ,  Yawei Wang ,  Chenyang Zhang ,  Chengfu Xu ,  Ce Ning ,  Pengxia Liang ,  Feihu Zhou ,  Xianqin Meng ,  Weiting Peng ,  Qiuli Wang ,  Binbin Tong ,  Rui Huang ,  Tianmin Zhou ,  Wei Yang

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L27/12

Abstract: A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the second electrode layer is disposed closer to the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer.

公开(公告)号：US12230683B2

公开(公告)日：2025-02-18

申请号：US17755380

申请日：2021-05-19

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lizhong Wang ,  Ce Ning ,  Hehe Hu ,  Tianmin Zhou ,  Jipeng Song

IPC: H01L29/786 ,  H01L29/417

Abstract: The present disclosure provides a thin film transistor, a GOA circuit and an array substrate, the thin film transistor including a source electrode, including a source electrode wiring and a plurality of source electrode branches; a drain electrode, including a drain electrode wiring and a plurality of drain electrode branches; a gate; a semiconductor layer including a plurality of semiconductor branches; a plurality of source electrode branches. The plurality of drain electrode branches are in contact with the plurality of semiconductor branches and are divided into a plurality of cells; the source electrode wiring and the drain electrode wiring are arranged in a parallel and spaced apart, and the number m of one of the source electrode wiring and the drain electrode wiring is an integer greater than or equal to 2, and the number n of the other is an integer greater than or equal to 1.

公开(公告)号：US11973094B2

公开(公告)日：2024-04-30

申请号：US17290495

申请日：2020-09-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Tianmin Zhou ,  Rui Huang ,  Wei Yang ,  Lizhong Wang ,  Zhaohui Qiang ,  Tao Yang ,  Li Qiang

IPC: H01L27/146 ,  G06V40/13 ,  H10K59/12 ,  H10K59/65 ,  H10K71/00

CPC classification number: H01L27/14616 ,  G06V40/1318 ,  H01L27/14603 ,  H01L27/14692 ,  H10K59/65 ,  H10K71/00 ,  H10K59/12 ,  H10K59/1201

Abstract: The present disclosure provides an array substrate, an electronic device and a manufacturing method of the array substrate. The array substrate includes a base substrate, and a first transistor and a second transistor on the base substrate, a first electrode of the first transistor being connected to a second electrode of the second transistor; the array substrate further includes a photodiode including a first electrode, a second electrode, and a photosensitive layer between the first electrode and the second electrode, and the first electrode is electrically connected to a gate of the first transistor. In the arrangement, the first transistor and the second transistor are connected in series to form one control unit, and the uniformity and stability of the control unit are greatly improved.

公开(公告)号：US20230091604A1

公开(公告)日：2023-03-23

申请号：US17611156

申请日：2021-01-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jie Huang ,  Jiayu He ,  Ce Ning ,  Zhengliang Li ,  Hehe Hu ,  Fengjuan Liu ,  Nianqi Yao ,  Kun Zhao ,  Tianmin Zhou ,  Jiushi Wang ,  Zhongpeng Tian

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

Abstract: The present disclosure relates to the field of display technologies, and in particular to a thin film transistor and a method for manufacturing the same, an array substrate and a display device. An active layer of the thin film transistor includes at least two metal oxide semi-conductor layers, the at least two metal oxide semi-conductor layers include a channel layer and a first protection layer, and metals in the channel layer include tin, and at least one of indium, gallium and zinc. The first protection layer includes praseodymium used to absorb photo-generated electrons from at least one of the channel layer and the first protection layer which is under light irradiation and reduce a photo-generated current caused by the light irradiation.

公开(公告)号：US12213372B2

公开(公告)日：2025-01-28

申请号：US17732781

申请日：2022-04-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wei Yang ,  Guangcai Yuan ,  Ce Ning ,  Xinhong Lu ,  Tianmin Zhou ,  Xin Yang

IPC: H01L51/00 ,  H10K59/124 ,  H10K59/131 ,  H10K77/10

Abstract: The present disclosure relates to an OLED display panel and display device. The OLED display panel includes: a display area, a bending area and a bonding area for bonding a circuit board, wherein the display panel further includes: a base substrate; a first semiconductor pattern on the base substrate; a first insulating layer group on the first semiconductor pattern; a second semiconductor pattern on the first insulating layer group; a second insulating layer group on the second semiconductor pattern; first via holes in the first insulating layer group and the second insulating layer group; second via holes in the second insulating layer group, wherein the display panel further includes: a first groove located in the bending area and having a depth substantially identical to that of the first via holes; and a metal trace, connecting a trace in the display area to the circuit board.