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公开(公告)号：US3649386A
公开(公告)日：1972-03-14
申请号：US3649386D
申请日：1968-04-23
Applicant: BELL TELEPHONE LABOR INC
Inventor： MURPHY BERNARD T
IPC: H01L29/93 , H01L21/00 , H01L21/283 , H01L21/316 , H01L21/329 , H01L21/762 , H01L23/29 , H01L29/00 , H01L29/74 , H01L29/864 , H01L29/866 , H01L7/44
CPC classification number: H01L23/29 , H01L21/00 , H01L21/76205 , H01L29/00 , H01L2924/0002 , Y10S148/03 , Y10S148/031 , Y10S148/085 , Y10S148/114 , Y10S148/117 , Y10S438/911 , H01L2924/00
Abstract: THE NVENTION IS A METHOD OF FABRICATING SEMICONDUCTOR DEVICES WHICH HAVE THE UNIFORM AVALANCHE BREAKDOWN JUNCTIONS CHARACTERISTIC OF PRIOR ART MESA DEVICE STRUCTURES WHILE RETAINING THE DESIRABLE PASSIVATION AND OVERLAY CONTACT FEATURES CHARACTERISTIC OF PLANAR STRUCTURES. AN IMPORTANT FEATURE IS BASED ON THE FACT THAT THE BULK INCREASES WHEN SILICON IS CONVERTED TO THE OXIDE WHEREBY DEPRESSIONS IN A SILICON BODY CAN BE FILLED BY SELECTIVE OXIDATION OF THE REGIONS OF THE DEPRESSIONS.
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2.发明授权Semiconductive memory array wherein operating power is supplied via information paths 失效通过信息栏提供操作电源的半导体存储器阵列
公开(公告)号：US3541531A
公开(公告)日：1970-11-17
申请号：US3541531D
申请日：1967-02-07
Applicant: BELL TELEPHONE LABOR INC
Inventor： IWERSEN JOHN E , MURPHY BERNARD T , WUORINEN JOHN H JR
IPC: G11C11/411 , G11C11/415 , G11C11/416 , G11C11/418 , G11C11/419 , H01L27/00 , H01L27/07 , H01L27/10 , H03K3/286 , H03K3/356 , G11C11/40
CPC classification number: H03K3/356 , G11C11/4116 , G11C11/415 , G11C11/416 , G11C11/418 , G11C11/419 , H01L27/00 , H01L27/0716 , H01L27/10 , H03K3/286 , Y10S148/037 , Y10S148/085
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3.发明授权Time scaled analog model test circuit for an active element and method of making such 失效用于主动元件的时间分段模拟模型测试电路及其制作方法
公开(公告)号：US3471786A
公开(公告)日：1969-10-07
申请号：US3471786D
申请日：1967-05-31
Applicant: BELL TELEPHONE LABOR INC
Inventor： GUMMEL HERMANN K , MURPHY BERNARD T
CPC classification number: G06G7/62
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4.发明授权Time-scaled test circuit for semiconductive element having a current controlled charge storage model 失效具有电流控制充电储存模型的半导体元件的时间测试电路
公开(公告)号：US3480864A
公开(公告)日：1969-11-25
申请号：US3480864D
申请日：1967-12-04
Applicant: BELL TELEPHONE LABOR INC
Inventor： MURPHY BERNARD T
CPC classification number: G06G7/62
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Patent Agency Ranking
公开(公告)号：US3413495A
公开(公告)日：1968-11-26
申请号：US42369465
申请日：1965-01-06
Applicant: BELL TELEPHONE LABOR INC
Inventor： MURPHY BERNARD T
IPC: H03K19/088
CPC classification number: H03K19/088
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公开(公告)号：US3394268A
公开(公告)日：1968-07-23
申请号：US42934565
申请日：1965-02-01
Applicant: BELL TELEPHONE LABOR INC
Inventor： MURPHY BERNARD T
IPC: H01L27/06 , H03K19/013 , H03K19/084
CPC classification number: H03K19/084 , H01L27/0652 , H03K19/013 , H03K19/0136
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公开(公告)号：US3653988A
公开(公告)日：1972-04-04
申请号：US3653988D
申请日：1969-04-03
Applicant: BELL TELEPHONE LABOR INC
Inventor： GLINSKI VINCENT J , MURPHY BERNARD T
IPC: H01L21/74 , H01L21/761 , H01L21/765 , H01L27/07 , H01L29/00 , H01L7/44 , B01J17/00 , H01L3/00
CPC classification number: H01L27/0716 , H01L21/74 , H01L21/761 , H01L21/765 , H01L29/00 , Y10S148/036 , Y10S148/037 , Y10S148/085 , Y10S438/919 , Y10S438/921
Abstract: This method of fabricating junction-isolated semiconductor integrated circuit devices eliminates the photolithographic masking operation associated with a base diffusion by performing a non-selective P-type base diffusion into the entire surface of a thin N-type epitaxial layer. The lateral extent of base zones and resistor zones is defined by selectively diffusing low resistivity N-type deep contact zones completely through the epitaxial layer to intersect the entire perimeter of a buried Nlayer. Junction isolation, consisting of either back-to-back diodes or junction field-effect transistors, may be used.
Abstract translation: 制造结隔离半导体集成电路器件的这种方法通过对薄N型外延层的整个表面进行非选择性P型基极扩散来消除与基极扩散相关的光刻掩模操作。 通过选择性地将低电阻率的N型深接触区域完全扩散通过外延层与掩埋的N层的整个周边相交，来限定基极区域和电阻器区域的横向范围。 可以使用由背对背二极管或结型场效应晶体管组成的结隔离。
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公开(公告)号：US3519751A
公开(公告)日：1970-07-07
申请号：US67357367
申请日：1967-10-09
Applicant: BELL TELEPHONE LABOR INC
Inventor： HARMS DAVID A , MURPHY BERNARD T
CPC classification number: H04B14/062 , H04Q11/04
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9.发明授权Method for producing semiconductor integrated circuit device and product produced thereby 失效生产半导体集成电路器件的方法及其生产的产品
公开(公告)号：US3575741A
公开(公告)日：1971-04-20
申请号：US3575741D
申请日：1968-02-05
Applicant: BELL TELEPHONE LABOR INC
Inventor： MURPHY BERNARD T
IPC: H01L21/74 , H01L21/761 , H01L27/06 , H01L7/64
CPC classification number: H01L21/743 , H01L21/761 , H01L27/0658 , Y10S148/036 , Y10S148/037 , Y10S148/085 , Y10S438/921
Abstract: IN THE FABRICATION OF A JUNCTION-ISOLATED SEMICONDUCTOR INTERGRATED CIRCUIT STRUCTURE, A PLURALITY OF N-TYPE BURIED LAYERS ARE DIFFUSED INTO A P-TYPE SUBSTRATE, AND A THIN PTYPE EPITAXIAL LAYER IS GROWN THEREOVER. N-TYPE DEEP CONTACT ZONES ARE DIFFUSED COMPLETELY THROUGH THE EPITAXIAL LAYER TO INTERSECT SEPARATE ONES OF THE N-TYPE BURIED LAYERS, THUS DEFINING BASE AREAS. P-TYPE IMPURITIES ARE THEN DIFFUSED NON-SELECTIVELY INTO THE ENTIRE SURFACE OF THE PTYPE EPITAXIAL LAYER TO FORM A GRADED IMPURITY PROFILE FOR THE BASE ZONE. N-TYPE EMITTER ZONES ARE THEN DIFFUSED SELECTIVELY INTO THE SURFACE.
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