知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

149 条记录 (耗时 0.012 秒)

    Logic circuits for forming VLSI logic networks
    1.
    发明授权
    Logic circuits for forming VLSI logic networks 失效
    用于形成VLSI逻辑网络的逻辑电路

    公开(公告)号：US4950927A

    公开(公告)日：1990-08-21

    申请号：US403062

    申请日：1989-09-05

    申请人： Gerard Boudon ,  Armand Brunin ,  Bernard Denis ,  Pierre Mollier ,  Philippe Stoppa

    发明人： Gerard Boudon ,  Armand Brunin ,  Bernard Denis ,  Pierre Mollier ,  Philippe Stoppa

    IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/06 ,  H03K19/003 ,  H03K19/082 ,  H03K19/084 ,  H03K19/088

    CPC分类号： H03K19/084 ,  H03K19/088

    摘要： A DTT type basic logic circuit exhibiting improved immunity to noise and including input diodes for receiving input signals A, B, . . .; an input transistor the emitter of which receives an additional input signal X and the base of which is connected to the anodes of the input diodes; and an output inverter transistor disposed so that the signal at the output thereof represents the logic function X(AB . . .). From this circuit, a family of logic circuits suitable for realizing very-large-scale-integration logic networks in a master slice can be developed. The master slice comprises general-purpose cells in which pre-diffused semiconductor elements can be interconnected to form the desired circuits.

    摘要翻译： 具有改进的抗噪声能力的DTT型基本逻辑电路，包括用于接收输入信号A，B的输入二极管。 。 。 输入晶体管，其发射极接收附加的输入信号X，其基极连接到输入二极管的阳极; 以及输出反相晶体管，其输出端的信号表示逻辑功能＆upbar＆X（AB ...）。 从该电路可以开发适合在主片中实现大规模集成逻辑网络的逻辑电路系列。 主切片包括通用单元，其中预扩散半导体元件可以互连以形成期望的电路。

    High-speed transistor with rectifying contact connected between base and collector
    2.
    发明授权
    High-speed transistor with rectifying contact connected between base and collector 失效
    具有整流接点的高速晶体管连接在基极和集电极之间

    公开(公告)号：US3909837A

    公开(公告)日：1975-09-30

    申请号：US15072071

    申请日：1971-06-07

    申请人： TEXAS INSTRUMENTS INC

    发明人： KRONLAGE JOHN WILLIAM

    IPC分类号： H01L21/00 ,  H01L23/48 ,  H01L23/482 ,  H01L27/00 ,  H01L27/07 ,  H01L29/08 ,  H03K19/08 ,  H03K19/084 ,  H01L29/48 ,  H01L27/02 ,  H01L29/56

    CPC分类号： H03K19/084 ,  H01L21/00 ,  H01L23/48 ,  H01L23/482 ,  H01L27/00 ,  H01L27/0766 ,  H01L29/0821 ,  H01L2924/0002 ,  H03K19/08 ,  H01L2924/00

    摘要： High-speed logic switching is accomplished by an internal antisaturation clamp comprising a barrier-type rectifying junction between the base electrode and a collector electrode of a junction transistor. Diffusion and metalization techniques are used to fabricate a shallow-base transistor, having a high internal cutoff frequency, and a barrier-type rectifying junction surrounded by a guard ring. The rectifying junction covers a window in a diffusion region for the base electrode over a portion of the collector electrode. A metal film overlays the window to the collector electrode area and extends over a portion of the base electrode, thereby forming a metal-semiconductor barrier-type rectifying junction internally between the base electrode and the collector electrode.

    摘要翻译： 高速逻辑切换是通过内部抗饱和钳来实现的，该内部抗饱和钳包括在基极和结晶体管的集电极之间的阻挡型整流结。 扩散和金属化技术用于制造具有高内部截止频率的浅基极晶体管和由保护环包围的阻挡型整流结。 整流结覆盖在集电极电极的一部分上的基极的扩散区域中的窗口。 金属膜将窗口覆盖到集电极电极区域并且在基极的一部分上延伸，从而在基极和集电极之间形成金属半导体势垒型整流结。

    Bidirectional digital amplifier
    3.
    发明授权
    Bidirectional digital amplifier 失效
    双向数字放大器

    公开(公告)号：US3882274A

    公开(公告)日：1975-05-06

    申请号：US44679774

    申请日：1974-02-28

    申请人： REGENTS STATE OF FLORIDA BOARD

    发明人： VICE WILLIAM E ,  BRODERSEN ARTHUR J ,  LIPOVSKI GERALD J

    IPC分类号： H03K5/02 ,  H03K17/62 ,  H03K19/084 ,  H03K19/177 ,  H04L25/24

    CPC分类号： H03K19/17736 ,  H03K5/02 ,  H03K17/6221 ,  H03K19/084 ,  H03K19/1778 ,  H03K19/17792

    摘要： This invention relates to a bi-directional digital amplifier for use in cellular switching circuits and in cellular computers and which is capable of propagating a signal in respectively opposite directions without degrading the signal and which is capable of delimiting such propagation in either or both directions. The amplifier requires no clock signals for operation, will not latch up in response to noise and is well suited for construction in the form of an integrated circuit chip.

    摘要翻译： 本发明涉及用于蜂窝式开关电路和蜂窝式计算机中的双向数字放大器，其能够分别相反地传播信号而不降低信号，并且能够在两个或两个方向上限定这种传播。 放大器不需要时钟信号进行操作，不会因噪声而被锁住，非常适合以集成电路芯片的形式构建。

    Logic gate circuit including a Schottky barrier diode
    4.
    发明授权
    Logic gate circuit including a Schottky barrier diode 失效
    逻辑门电路包括肖特基势垒二极管

    公开(公告)号：US3869622A

    公开(公告)日：1975-03-04

    申请号：US28744772

    申请日：1972-09-08

    申请人： NIPPON ELECTRIC CO

    发明人： SHIMIZU KYOZO

    IPC分类号： H01L27/06 ,  H01L21/8222 ,  H01L27/07 ,  H03K19/082 ,  H03K19/084 ,  H01L19/00

    CPC分类号： H01L27/0755 ,  H03K19/084

    摘要： A logic gate circuit that is highly suitable for incorporation in a large scale integrated circuit includes a transistor having a base electrode connected to the input terminal, an emitter electrode connected to a voltage source, and a collector electrode. A Schottky barrier diode is connected between the collector electrode and the output terminal.

    摘要翻译： 高度适合并入大规模集成电路的逻辑门电路包括具有连接到输入端的基极，连接到电压源的发射极和集电极的晶体管。 在集电极与输出端子之间连接有肖特基势垒二极管。

    Transistor logic circuit with upset feedback
    5.
    发明授权
    Transistor logic circuit with upset feedback 失效
    带逆变器的晶体管逻辑电路

    公开(公告)号：US3654486A

    公开(公告)日：1972-04-04

    申请号：US3654486D

    申请日：1970-05-26

    申请人： SPERRY RAND CORP

    发明人： CUBERT JACK S

    IPC分类号： H03K3/2893 ,  H03K19/013 ,  H03K19/084 ,  H03K19/40 ,  H03K19/22 ,  H03K19/30

    CPC分类号： H03K19/084 ,  H03K3/2893 ,  H03K19/013

    摘要： The invention includes a semiconductor circuit and in one mode comprises two transistors wherein the first operates as a common emitter whereas the second operates as an emitter follower. When the first transistor is in a non-conducting state and the second is conducting, the input level of the first is raised to almost the conduction level by a negative feedback signal. During the time that the first transistor is turned on (the transitory period), a relatively positive feedback signal after which a negative feedback signal is provided thereto. The latter signal prevents saturation of the first transistor.

    摘要翻译： 本发明包括半导体电路，并且在一种模式中包括两个晶体管，其中第一晶体管作为共发射极工作，而第二晶体管作为射极跟随器工作。 当第一晶体管处于非导通状态并且第二晶体管导通时，第一晶体管的输入电平通过负反馈信号升高到几乎导通电平。 在第一晶体管导通（暂时期）的时间期间，相对正的反馈信号在其之后提供负反馈信号。 后一种信号防止第一晶体管的饱和。