公开(公告)号：US4123669A

公开(公告)日：1978-10-31

申请号：US831582

申请日：1977-09-08

申请人： William T. Devine ,  William F. Washburn

发明人： William T. Devine ,  William F. Washburn

IPC分类号： H03K19/017 ,  H03K19/0944 ,  H03K19/177 ,  H03K19/20 ,  H03K19/08 ,  G06F9/00 ,  H03K17/04 ,  H03K19/30

CPC分类号： H03K19/09443 ,  H03K19/017 ,  H03K19/1772

摘要： An improved logical OR circuit is shown wherein the load resistance is divided into drain resistance and source resistance, each resistance having a lower value than could be employed with a single load resistance while at the same time keeping power dissipation to low levels. The use of relatively lower resistances permits faster voltage rise time, thereby permitting faster programmed logic array (PLA) operation. The voltage drop across the source resistance is made small when the output device is conducting by providing a substantially higher drain resistance load for the output device with respect to the drain resistance of the input devices.

摘要翻译： 示出了改进的逻辑或电路，其中负载电阻被分为漏极电阻和源极电阻，每个电阻具有比单个负载电阻可以使用的更低的值，同时将功率耗散保持在低电平。 使用相对较低的电阻允许更快的电压上升时间，从而允许更快的编程逻辑阵列（PLA）操作。 当输出装置导通时，通过相对于输入装置的漏极电阻提供输出装置的显着更高的漏极电阻负载，使源极电阻上的电压降小。

公开(公告)号：US3758791A

公开(公告)日：1973-09-11

申请号：US3758791D

申请日：1970-06-04

申请人： HITACHI LTD

发明人： TANIGUCHI K ,  IMAIZUMI I

IPC分类号： H03K17/14 ,  H03K19/086 ,  H03K19/30 ,  H03K19/34

CPC分类号： H03K17/14 ,  H03K19/086

摘要： A current switch circuit consisting of a couple of transistors, one transistor acting as a reference element and the other as an input element, a pair of series connections of a resistance element and a diode being connected between the respective collectors of the said transistors with the polarity of the diodes opposite to each other, so that the emitter current of the transistors are automatically regulated to maintain a predetermined value, whereby the DC levels of the output voltages of the current switch circuit are kept constant against temperature variation of the transistors.

摘要翻译： 由一对晶体管组成的电流开关电路，一个用作参考元件的晶体管，另一个用作输入元件，电阻元件和二极管的一对串联连接连接在所述晶体管的各个集电极之间， 二极管的极性彼此相反，使得晶体管的发射极电流被自动调节以保持预定值，由此电流开关电路的输出电压的DC电平保持恒定，抵抗晶体管的温度变化。

公开(公告)号：US3634876A

公开(公告)日：1972-01-11

申请号：US3634876D

申请日：1970-08-21

申请人： RCA CORP

发明人： YORGANJIAN JOHN JAMES

IPC分类号： G11C11/06 ,  H03K3/027 ,  H03K3/30 ,  H03K19/173 ,  H03K19/24 ,  H03K19/30 ,  H03K19/34

CPC分类号： G11C11/06007 ,  H03K3/027 ,  H03K3/30 ,  H03K19/173

摘要： A sense signal detecting and latching circuit is disclosed which can be coupled to the output of a differential sense amplifier to provide a memory data register. An enable pulse, having a leading edge occurring before a sense signal to be detected and having a trailing edge occuring at a predetermined time following the end of the sense signal, is applied to one input of a coincidence gate. A transformer has a primary winding coupled to output terminals of the differential sense amplifier and has one end of its secondary winding connected to another input of the coincidence gate. The other end of the secondary winding is connected to an output terminal of the coincidence gate having a polarity to provide positive feedback through the secondary winding to the input of the coincidence gate. The coincidence gate responds to a sense signal to provide an output signal which is maintained until the time of the end of the enable pulse.

摘要翻译： 公开了一种感测信号检测和锁存电路，其可以耦合到差分读出放大器的输出以提供存储器数据寄存器。 一个使能脉冲被施加到符合栅极的一个输入端上，该前沿在检测到的检测信号之前出现，并且在感测信号结束之后的预定时间发生后沿。 变压器具有耦合到差分读出放大器的输出端的初级绕组，并且其次级绕组的一端连接到重合门的另一个输入端。 次级绕组的另一端连接到具有极性的符合栅极的输出端，以通过次级绕组向符合栅极的输入提供正反馈。 符合门响应于感测信号以提供维持直到使能脉冲结束的时间的输出信号。

公开(公告)号：US3596107A

公开(公告)日：1971-07-27

申请号：US3596107D

申请日：1969-07-09

申请人： COLLINS RADIO CO

发明人： KITTRELL RICHARD L

IPC分类号： G01R19/00 ,  H03K19/30

CPC分类号： G01R19/0038

摘要： A signal selecting means to which a plurality of signals of variable amplitude and sign are applied and which develops an output signal corresponding in magnitude and sign to preselected ones, depending on algebraic rank, of the midvalue applied signals, exclusive of the most algebraically positive and negative ones of the input signals. The output signal magnitude is controlled by a predetermined permutation of midvalue selections and in a manner that obviates transients on the output line as control is transferred to the various ones of the midvalue input signals.

公开(公告)号：US3510679A

公开(公告)日：1970-05-05

申请号：US3510679D

申请日：1966-10-26

申请人： GEN ELECTRIC

发明人： PEIL WILLIAM

IPC分类号： H03K3/037 ,  H03K3/315 ,  H03K19/086 ,  H03K19/08 ,  H03K19/22 ,  H03K19/30

CPC分类号： H03K3/0377 ,  H03K3/037 ,  H03K3/315 ,  H03K19/086

公开(公告)号：US3916217A

公开(公告)日：1975-10-28

申请号：US45806174

申请日：1974-04-04

申请人： HITACHI LTD

发明人： SHIMADA SHUNJI ,  HATSUKANO YOSHIKAZU

IPC分类号： H03K19/0175 ,  H03K19/0185 ,  H03K19/096 ,  H03K19/173 ,  H03K19/08 ,  H03K5/13 ,  H03K19/30 ,  H03K19/40

CPC分类号： H03K19/018557 ,  H03K19/0963 ,  H03K19/173

摘要： An integrated logical circuit device for providing a wired ''''OR'''' logic function between chips or circuit devices which include logical circuits of the ratioless type, comprises ''''floating'''' circuits and OR gate circuits which are formed within the corresponding chips or circuit devices. Each floating circuit determines the level of an output signal in dependence on a signal from the logical circuit at a prescribed time and makes its output terminal floating at another time. The OR gate circuits receive the output signal at the prescribed time and a signal from the logical circuit at the another time, to provide a wired OR circuit.

摘要翻译： 一种集成逻辑电路装置，用于在包括无竞争类型的逻辑电路的芯片或电路装置之间提供有线“或”逻辑功能，包括形成在相应芯片或电路装置内的“浮动”电路和“或”门电路。 每个浮动电路根据来自逻辑电路的信号在规定时间确定输出信号的电平，并使其输出端在另一时间浮置。 OR门电路在规定时间接收输出信号，并在另一时间接收来自逻辑电路的信号，以提供有线OR电路。

公开(公告)号：US3780317A

公开(公告)日：1973-12-18

申请号：US3780317D

申请日：1971-07-29

申请人： FUJITSU LTD

发明人： KURATA T ,  ORITANI A

IPC分类号： H03K5/08 ,  H03K5/24 ,  H03K5/20 ,  H03K19/30

CPC分类号： H03K5/2445 ,  H03K5/2418

摘要： A comparator circuit comprises a differential amplifier for providing the difference between signals supplied to its inputs. An amplifier and pulse shaper has a transistor connected to the differential amplifier for amplifying and shaping the output signal of the differential amplifier. An impedance converter connected to the output of the amplifier and pulse shaper transistor transmits output signals at low output impedance. A negative feedback path is provided between the output of the impedance converter and the input of the amplifier and pulse shaper transistor. The negative feedback path is operational when the voltage between its input and output is substantially zero and is non-operational when the voltage between its input and output is different from zero.

摘要翻译： 比较器电路包括用于提供提供给其输入的信号之间的差的差分放大器。 放大器和脉冲整形器具有连接到差分放大器的晶体管，用于放大和整形差分放大器的输出信号。 连接到放大器和脉冲整形器晶体管的输出端的阻抗转换器以低输出阻抗传输输出信号。 在阻抗转换器的输出与放大器和脉冲整形晶体管的输入之间提供负反馈路径。 当负输入和输出之间的电压基本为零时，负反馈路径是可操作的，当输入和输出之间的电压不为零时，负反馈路径是不可操作的。

公开(公告)号：US3740652A

公开(公告)日：1973-06-19

申请号：US3740652D

申请日：1971-11-17

申请人： MONSANTO CO

发明人： BURGENER W

IPC分类号： G01R19/165 ,  G01R19/00 ,  G01R19/32 ,  G05B7/02 ,  G06G7/12 ,  H03K17/74 ,  H03K19/30

CPC分类号： G01R19/0038

摘要： Described herein is an analog signal selector circuit including an input circuit comprising two arrays of semiconductor diodes, all having substantially identical forward-bias characteristics, and an input circuit comprising a noninverting operational amplifier having a feedback loop, in which is operatively connected a forward-biased semi-conductor diode having characteristics matched to those of the two diode arrays. The arrays are connected to input terminals to which discrete analog input signals (DC) are applied. Selective actuation of the diode arrays results in the highest or lowest of the input signals being selected and applied to the operational amplifier, the output of which precisely reproduces the selected input signal, notwithstanding variations in the electrical characteristics of the array diodes as a result of temperature changes.

摘要翻译： 这里描述的模拟信号选择器电路包括一个包括两个半导体二极管阵列的输入电路，全部具有基本上相同的正向偏置特性，以及包括具有反馈回路的同相运算放大器的输入电路， 具有与两个二极管阵列相匹配的特性的偏置半导体二极管。 阵列连接到应用了分立模拟输入信号（DC）的输入端子。 二极管阵列的选择性驱动导致选择和施加到运算放大器的输入信号的最高或最低，其运算放大器的输出精确地再现所选择的输入信号，尽管由于阵列二极管的电特性的变化，由于 温度变化。

公开(公告)号：US3714465A

公开(公告)日：1973-01-30

申请号：US3714465D

申请日：1972-01-14

申请人： SKRENES D

发明人： SKRENES D

IPC分类号： G01R19/165 ,  G01R19/00 ,  G06K9/62 ,  H03K5/20 ,  G06G7/14 ,  H03K19/30

CPC分类号： G01R19/0038

摘要： An analog decision circuit for analyzing a group of analog signals and identifying and ordering these signals according to their magnitudes. A first analog signal OR circuit identifies the largest magnitude analog signal and by means of a feedback circuit, this signal is eliminated from a second analog signal OR circuit which identifies the next largest analog signal. A second feedback circuit eliminates the second largest analog signal from the input of a third analog signal OR circuit which identifies the third largest analog signal. Similar circuitry is provided for each additional analog signal. Comparator circuits are also included to determine the separation between one largest analog signal and the next largest signal.

摘要翻译： 一种用于分析一组模拟信号并根据其幅度识别和排序这些信号的模拟判决电路。 第一模拟信号或电路识别最大幅度的模拟信号，并借助于反馈电路，从识别下一最大模拟信号的第二模拟信号或电路中消除该信号。 第二反馈电路消除了识别第三大模拟信号的第三模拟信号或电路的输入的第二大模拟信号。 为每个附加模拟信号提供类似的电路。 还包括比较器电路以确定一个最大模拟信号和下一个最大信号之间的间隔。

公开(公告)号：US3668430A

公开(公告)日：1972-06-06

申请号：US3668430D

申请日：1971-07-12

申请人： SIGNETICS CORP

发明人： KAN DAVID T

IPC分类号： H03K19/013 ,  H03K19/018 ,  H03K19/30 ,  H03K19/34

CPC分类号： H03K19/013 ,  H03K19/01812

摘要： A high speed logic circuit includes a differential amplifier driving a shunt feedback output amplifier having an input which acts as an ac ground. The effective Miller capacitance of the differential amplifier is therefore minimized.

摘要翻译： 高速逻辑电路包括驱动具有作为交流地的输入的并联反馈输出放大器的差分放大器。 因此，差分放大器的有效米勒电容最小化。