公开(公告)号：US3714465A

公开(公告)日：1973-01-30

申请号：US3714465D

申请日：1972-01-14

申请人： SKRENES D

发明人： SKRENES D

IPC分类号： G01R19/165 ,  G01R19/00 ,  G06K9/62 ,  H03K5/20 ,  G06G7/14 ,  H03K19/30

CPC分类号： G01R19/0038

摘要： An analog decision circuit for analyzing a group of analog signals and identifying and ordering these signals according to their magnitudes. A first analog signal OR circuit identifies the largest magnitude analog signal and by means of a feedback circuit, this signal is eliminated from a second analog signal OR circuit which identifies the next largest analog signal. A second feedback circuit eliminates the second largest analog signal from the input of a third analog signal OR circuit which identifies the third largest analog signal. Similar circuitry is provided for each additional analog signal. Comparator circuits are also included to determine the separation between one largest analog signal and the next largest signal.

摘要翻译： 一种用于分析一组模拟信号并根据其幅度识别和排序这些信号的模拟判决电路。 第一模拟信号或电路识别最大幅度的模拟信号，并借助于反馈电路，从识别下一最大模拟信号的第二模拟信号或电路中消除该信号。 第二反馈电路消除了识别第三大模拟信号的第三模拟信号或电路的输入的第二大模拟信号。 为每个附加模拟信号提供类似的电路。 还包括比较器电路以确定一个最大模拟信号和下一个最大信号之间的间隔。