公开(公告)号：US4495626A

公开(公告)日：1985-01-22

申请号：US391813

申请日：1982-06-24

申请人： Armand Brunin ,  Guy D'Hervilly

发明人： Armand Brunin ,  Guy D'Hervilly

IPC分类号： H04L25/02 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/21 ,  H03K19/23 ,  H04L25/08 ,  H04L25/12 ,  H04L25/34

CPC分类号： H04L25/0272 ,  H03K19/00346 ,  H03K19/01806 ,  H03K19/212 ,  H03K19/23 ,  H04L25/12

摘要： A method and electronic network for limiting the electrical noise arising during transmission of digital data signals from a first integrated circuit having multiple output devices at which the data signals are formed to the input of a second integrated circuit. The method and network feature steps and means for sensing the conduction state of the first integrated circuit devices and for generating a control signal to invert the data signals before transmission when the number of output devices conducting is equal to or greater than a predetermined number. The method and network also feature steps and means for transmitting the data signals and control signal so that the data signals may be reconstituted to establish the data signals as they appear at the first integrated circuit output, before the data signals are presented to the second integrated circuit input.

摘要翻译： 一种方法和电子网络，用于限制在具有多个输出装置的第一集成电路的数字数据信号传输期间产生的电噪声，在该第一集成电路上形成数据信号至第二集成电路的输入端。 该方法和网络特征步骤和装置用于感测第一集成电路装置的导通状态，并且用于在输出装置的数量等于或大于预定数量时产生控制信号以反转传输之前的数据信号。 所述方法和网络还具有用于发送数据信号和控制信号的步骤和装置，使得数据信号可以被重构以便在数据信号被呈现给第二集成电路时在第一集成电路输出处出现时建立数据信号 电路输入。

公开(公告)号：US4942316A

公开(公告)日：1990-07-17

申请号：US275860

申请日：1988-11-25

申请人： Herve Beranger ,  Armand Brunin ,  Bruno Caplier ,  Jean-Paul Rousseau

发明人： Herve Beranger ,  Armand Brunin ,  Bruno Caplier ,  Jean-Paul Rousseau

IPC分类号： H03K3/289 ,  H03K19/0185 ,  H03K19/086 ,  H03K19/173

CPC分类号： H03K19/018514 ,  H03K19/0866 ,  H03K19/1738 ,  H03K3/289

摘要： A logic circuit family derived from the conventional 2 level single-ended cascode logic circuit. The basic logic circuit performing a 2--2 OA/AI logic function shown in the attached drawing is given for illustration purposes. It comprises: a logic tree 35 comprised of top and bottom stages 37, 36 dotted at the tree output 38 to perform a determined logic function; the top stage 37 includes a current switch comprised of two input transistors TX34, TX35 connected in a differential amplifier configuration with a reference transistor TX36. The bases of input transistors TX34, TX35 are provided with at least two level shifter devices. Preferably, input level shifter devices are Schottky diodes P31, . . . which move the voltages towards the more positive voltage VPP, to add an AND function on each of these input transistors.

摘要翻译： 一种来自传统的2级单端串联逻辑电路的逻辑电路系列。 为了说明的目的，给出了执行附图中所示的2-2 OA / AI逻辑功能的基本逻辑电路。 它包括：逻辑树35，其由顶部和底部阶段37,36组成，其点缀在树形输出38以执行确定的逻辑功能; 顶级37包括由以差分放大器配置连接到参考晶体管TX36的两个输入晶体管TX34，TX35组成的电流开关。 输入晶体管TX34，TX35的基极设置有至少两个电平移位器装置。 优选地，输入电平转换器件是肖特基二极管P31。 。 。 其将电压移向更正的正电压VPP，以在这些输入晶体管的每一个上添加AND功能。

公开(公告)号：US4592023A

公开(公告)日：1986-05-27

申请号：US623052

申请日：1984-06-21

申请人： Herve Beranger ,  Armand Brunin ,  Jean-Paul Rousseau

发明人： Herve Beranger ,  Armand Brunin ,  Jean-Paul Rousseau

IPC分类号： H04B14/04 ,  G11C11/411 ,  H03K3/288 ,  G11C7/00

CPC分类号： H03K3/288 ,  G11C11/4113

摘要： A latch that can serve as a bit storage cell in a random-access store. The latch includes an AND gate (diodes D1 and D2) the input IN of which receives the bit to be stored and the other input of which is connected to a write control line WRL. When no write operation is being performed, transistor T1 is turned off and the state of transistor T2 is dependent on output potential OUT. To perform a write operation, line WRL is activated (goes high) and the state of transistor T3 will depend on the value of the bit applied to input IN. Read operations are performed by means of another AND gate (diodes D4 and D5) and an emitter follower (transistor T4) connected via a bit line BL to an output circuit 2. By adding input transistors and emitter followers to the latch, a multi-port storage can be realized, several rows of which can be simultaneously written into and/or read out.

摘要翻译： 可以作为随机存取存储区中的位存储单元的锁存器。 锁存器包括与门（二极管D1和D2），其输入端IN接收待存储的位，其另一个输入端连接到写控制线WRL。 当不执行写入操作时，晶体管T1截止，晶体管T2的状态取决于输出电位OUT。 为了执行写操作，线WRL被激活（变高），晶体管T3的状态将取决于施加到输入IN的位的值。 通过另一个与门（二极管D4和D5）和经由位线BL连接到输出电路2的射极跟随器（晶体管T4）执行读取操作。通过将输入晶体管和发射极跟随器添加到锁存器， 可以实现端口存储，其中几行可以被同时写入和/或读出。

公开(公告)号：US4950927A

公开(公告)日：1990-08-21

申请号：US403062

申请日：1989-09-05

申请人： Gerard Boudon ,  Armand Brunin ,  Bernard Denis ,  Pierre Mollier ,  Philippe Stoppa

发明人： Gerard Boudon ,  Armand Brunin ,  Bernard Denis ,  Pierre Mollier ,  Philippe Stoppa

IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/06 ,  H03K19/003 ,  H03K19/082 ,  H03K19/084 ,  H03K19/088

CPC分类号： H03K19/084 ,  H03K19/088

摘要： A DTT type basic logic circuit exhibiting improved immunity to noise and including input diodes for receiving input signals A, B, . . .; an input transistor the emitter of which receives an additional input signal X and the base of which is connected to the anodes of the input diodes; and an output inverter transistor disposed so that the signal at the output thereof represents the logic function X(AB . . .). From this circuit, a family of logic circuits suitable for realizing very-large-scale-integration logic networks in a master slice can be developed. The master slice comprises general-purpose cells in which pre-diffused semiconductor elements can be interconnected to form the desired circuits.

摘要翻译： 具有改进的抗噪声能力的DTT型基本逻辑电路，包括用于接收输入信号A，B的输入二极管。 。 。 输入晶体管，其发射极接收附加的输入信号X，其基极连接到输入二极管的阳极; 以及输出反相晶体管，其输出端的信号表示逻辑功能＆upbar＆X（AB ...）。 从该电路可以开发适合在主片中实现大规模集成逻辑网络的逻辑电路系列。 主切片包括通用单元，其中预扩散半导体元件可以互连以形成期望的电路。

公开(公告)号：US4430737A

公开(公告)日：1984-02-07

申请号：US342875

申请日：1982-01-26

申请人： Herve Beranger ,  Armand Brunin

发明人： Herve Beranger ,  Armand Brunin

IPC分类号： H03K19/21 ,  G06F11/10

CPC分类号： H03K19/212

摘要： An Exclusive OR circuit with at least two inputs (1 and 2) which exhibits a good immunity to noise. The circuit comprises diodes (D1 and D2) and two transistors (T1 and T2) which have their emitters connected to a reference voltage VR and produce AB at C1. Transistors (T 14 and T5) produce AB at C2, and output transistors (T13 and T6) produce ##STR1## at 3. This circuit can advantageously be used to realize a parity checking circuit.

摘要翻译： 具有至少两个输入（1和2）的异或电路，具有良好的抗噪声能力。 电路包括二极管（D1和D2）和两个晶体管（T1和T2），它们的发射极连接到参考电压VR并在C1产生AB。 晶体管（T14和T5）在C2处产生AB，输出晶体管（T13和T6）在3处产生。该电路可有利地用于实现奇偶校验电路。