公开(公告)号：US11049760B2

公开(公告)日：2021-06-29

申请号：US15436936

申请日：2017-02-20

Applicant: Applied Materials, Inc.

Inventor： Olivier Joubert ,  Jason A. Kenney ,  Sunil Srinivasan ,  James Rogers ,  Rajinder Dhindsa ,  Vedapuram S. Achutharaman ,  Olivier Luere

IPC: H01L21/687 ,  H01J37/32 ,  H01L21/683

Abstract: The implementations described herein generally relate to a process kit suitable for use in a semiconductor process chamber, which reduces edge effects and widens the processing window with a single edge ring as compared to conventional process kits. The process kit generally includes an edge ring disposed adjacent to and surrounding a perimeter of a semiconductor substrate in a plasma chamber. A dimension of a gap between the substrate and the edge ring is less than about 1000 μm, and a height difference between the substrate and the edge ring is less than about (+/−) 300 μm. The resistivity of the ring is less than about 50 Ohm-cm.

公开(公告)号：US10062602B2

公开(公告)日：2018-08-28

申请号：US14142124

申请日：2013-12-27

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  CNRS Centre National de la Recherche Scientifique ,  APPLIED MATERIALS, Inc.

Inventor： Nicolas Posseme ,  Sebastien Barnola ,  Olivier Joubert ,  Srinivas Nemani ,  Laurent Vallier

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76802 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76814 ,  H01L2221/1063

Abstract: The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at least one silicon-based gas mixed with oxygen (O2) and/or nitrogen (N2) so as to grow a passivation layer all along said etching, at least on flanks of the layer of porous dielectric material and wherein the silicon-based gas is taken from all the compounds of the type SixHy for which the ratio x/y is equal or greater than 0.3 or is taken from all the compounds of the following types: SixFy and SixCly, where x is the proportion of silicon (Si) in the gas and y is the proportion of fluorine (F) or chlorine (Cl) or hydrogen (H) in the gas.

公开(公告)号：US11728124B2

公开(公告)日：2023-08-15

申请号：US17377639

申请日：2021-07-16

Applicant: APPLIED MATERIALS, INC.

Inventor： Leonid Dorf ,  Travis Koh ,  Olivier Luere ,  Olivier Joubert ,  Philip A. Kraus ,  Rajinder Dhindsa ,  James Rogers

IPC: H01J37/08 ,  H01J37/248 ,  H01J37/32

CPC classification number: H01J37/08 ,  H01J37/248 ,  H01J37/32577 ,  H01J37/32706 ,  H01J37/32715

Abstract: Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse-bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.

公开(公告)号：US09975758B2

公开(公告)日：2018-05-22

申请号：US15649597

申请日：2017-07-13

Applicant: Applied Materials, Inc.

Inventor： Leonard Tedeschi ,  Lili Ji ,  Olivier Joubert ,  Dmitry Lubomirsky ,  Philip Allan Kraus ,  Daniel T. McCormick

IPC: H01L27/146 ,  B81B7/00 ,  H01L21/67 ,  B81C1/00

CPC classification number: B81B7/0058 ,  B81B2201/047 ,  B81C1/00031 ,  B81C1/00412 ,  C23C16/4401 ,  C23C16/52 ,  H01L21/67288

Abstract: Embodiments include devices and methods for detecting particles, monitoring etch or deposition rates, or controlling an operation of a wafer fabrication process. In an embodiment, one or more micro sensors are mounted on wafer processing equipment, and are capable of measuring material deposition and removal rates in real-time. The micro sensors are selectively exposed such that a sensing layer of a micro sensor is protected by a mask layer during active operation of another micro sensor, and the protective mask layer may be removed to expose the sensing layer when the other micro sensor reaches an end-of-life. Other embodiments are also described and claimed.

公开(公告)号：US11069504B2

公开(公告)日：2021-07-20

申请号：US16867034

申请日：2020-05-05

Applicant: APPLIED MATERIALS, INC.

Inventor： Leonid Dorf ,  Travis Koh ,  Olivier Luere ,  Olivier Joubert ,  Philip A. Kraus ,  Rajinder Dhindsa ,  James Rogers

IPC: H01J37/08 ,  H01J37/32 ,  H01J37/248

Abstract: Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse—bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.

公开(公告)号：US10685807B2

公开(公告)日：2020-06-16

申请号：US16405377

申请日：2019-05-07

Applicant: APPLIED MATERIALS, INC.

Inventor： Leonid Dorf ,  Travis Koh ,  Olivier Luere ,  Olivier Joubert ,  Philip A. Kraus ,  Rajinder Dhindsa ,  James Rogers

IPC: H01J37/08 ,  H01J37/24 ,  H01J37/248 ,  H01J37/32

Abstract: Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse-bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.

公开(公告)号：US10312048B2

公开(公告)日：2019-06-04

申请号：US15834939

申请日：2017-12-07

Applicant: APPLIED MATERIALS, INC.

Inventor： Leonid Dorf ,  Travis Koh ,  Olivier Luere ,  Olivier Joubert ,  Philip A. Kraus ,  Rajinder Dhindsa ,  James Hugh Rogers

IPC: H01J37/08 ,  C23C14/54 ,  C23C16/50 ,  H01J37/248

Abstract: Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse-bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.

公开(公告)号：US10109464B2

公开(公告)日：2018-10-23

申请号：US15335074

申请日：2016-10-26

Applicant: Applied Materials, Inc.

Inventor： Olivier Joubert ,  Olivier Luere ,  Vedapuram S. Achutharaman

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/687 ,  C23C4/02 ,  C23C4/10 ,  C23C4/00 ,  C23C4/134 ,  C23C16/40 ,  C23C16/44

Abstract: Methods are disclosed for etching a substrate. The method includes preferentially coating cover ring relative other chamber components in the processing chamber, while under vacuum, and while a substrate is not present in the processing chamber. The substrate is subsequently etched the processing chamber. After etching, the interior of the processing chamber is cleaned after the substrate has been removed.

公开(公告)号：US20160300709A1

公开(公告)日：2016-10-13

申请号：US15091916

申请日：2016-04-06

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  CNRS Centre National de la Recherche Scientifique ,  APPLIED MATERIALS, Inc.

Inventor： Nicolas POSSEME ,  Thibaut David ,  Olivier Joubert ,  Thorsten Lill ,  Srinivas Nemani ,  Laurent Vallier

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/306

CPC classification number: H01L21/0234 ,  H01L21/0217 ,  H01L21/02321 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L29/66628 ,  H01L29/66772

Abstract: A method is provided for forming spacers for a gate of a field effect transistor, the gate being situated above a layer of semiconductor material, including forming a layer of nitride covering the gate; modifying the layer by plasma implantation of light ions, having an atomic number equal or less than 10, in the layer in order to form a modified layer of nitride, the modifying being performed so as not to modify the layer of nitride over its entire thickness at flanks of the gate; and removing the modified layer of nitride by a selective wet or dry etching, of the modified layer relative to said layer of semiconductor material and relative to the non-modified layer at the flanks of the gate, without etching the layer of semiconductor material, wherein an entire length of the non-modified layer at the flanks remains after the selective wet or dry etching.

Abstract translation: 提供一种用于形成场效应晶体管的栅极的间隔物的方法，栅极位于半导体材料层之上，包括形成覆盖栅极的氮化物层; 通过在层中等离子体注入原子数等于或小于10的光离子来修饰层，以便形成改性的氮化物层，进行修饰以在其整个厚度上不改变氮化物层 在门的侧面; 以及通过选择性湿法或干法蚀刻，相对于所述半导体材料层和相对于栅极侧面处的非改性层，相对于未改性层，通过选择性湿法或干蚀刻去除修饰的氮化物层，而不蚀刻半导体材料层，其中 在选择性湿法或干蚀刻之后，侧面上未改性层的整个长度保留。

公开(公告)号：US09257293B2

公开(公告)日：2016-02-09

申请号：US14205673

申请日：2014-03-12

Applicant: Applied Materials, Inc.

Inventor： Nicolas Posseme ,  Olivier Joubert ,  Thibaut David ,  Thorsten Lill

IPC: H01L21/00 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3105

CPC classification number: H01L21/3065 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/7834

Abstract: Embodiments of methods of forming silicon nitride spacers are provided herein. In some embodiments, a method of forming silicon nitride spacers atop a substrate includes: depositing a silicon nitride layer atop an exposed silicon containing layer and an at least partially formed gate stack disposed atop a substrate; modifying a portion of the silicon nitride layer by exposing the silicon nitride layer to a hydrogen or helium containing plasma that is substantially free of fluorine; and removing the modified portion of the silicon nitride layer by performing a wet cleaning process to form the silicon nitride spacers, wherein the wet cleaning process removes the modified portion of the silicon nitride layer selectively to the silicon containing layer.

Abstract translation: 本文提供了形成氮化硅间隔物的方法的实施例。 在一些实施例中，在衬底顶部形成氮化硅间隔物的方法包括：在暴露的含硅层和设置在衬底顶部的至少部分形成的栅极堆叠之上沉积氮化硅层; 通过将氮化硅层暴露于基本上不含氟的含氢或含氦的等离子体来修饰氮化硅层的一部分; 以及通过进行湿式清洗处理来形成所述氮化硅间隔物来去除所述氮化硅层的修饰部分，其中所述湿式清洁工艺选择性地将所述氮化硅层的修饰部分去除所述含硅层。