知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

26 records (took 0.06 seconds)

    Method and apparatus for encoding erroneous data in an error correction code protected memory
    1.
    发明授权
    Method and apparatus for encoding erroneous data in an error correction code protected memory 有权
    用于对纠错码保护存储器中的错误数据进行编码的方法和装置

    公开(公告)号：US09354970B2

    公开(公告)日：2016-05-31

    申请号：US14230115

    申请日：2014-03-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ross V. La Fetra ,  Vilas K. Sridharan ,  Vydhyanathan Kalyanasundharam ,  Dean A. Liberty ,  Amit P. Apte

    IPC: G06F11/10 ,  H04L1/00 ,  H04L27/00 ,  G11B20/18 ,  G11C29/52

    CPC classification number: G06F11/1076 ,  G06F11/10 ,  G11B20/1833 ,  G11C29/52 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0071 ,  H04L2027/0036

    Abstract: A method and device are described for encoding erroneous data in an error correction code (ECC) protected memory. In one embodiment, incoming data including a plurality of data symbols and a data integrity marker is received. At least one extra symbol is used to mark the incoming data as error-free data or erroneous data (i.e., poison) based on the data integrity marker. ECC may be created to protect the data symbols. The ECC may include a plurality of check symbols, a plurality of unused symbols and the at least one extra symbol. In another embodiment, an error marker may be propagated from a single ECC word to all ECC words of data block (e.g., a cache line, a page, and the like) to prevent errors due to corruption of the error marker caused by faulty memory in the erroneous ECC word.

    Abstract translation: 描述了用于对纠错码（ECC）保护存储器中的错误数据进行编码的方法和装置。 在一个实施例中，接收包括多个数据符号和数据完整性标记的输入数据。 使用至少一个额外的符号来将输入数据标记为基于数据完整性标记的无错误数据或错误数据（即毒药）。 可以创建ECC以保护数据符号。 ECC可以包括多个检查符号，多个未使用的符号和至少一个额外的符号。 在另一个实施例中，错误标记可以从单个ECC字传播到数据块的所有ECC字（例如，高速缓存线，页等），以防止由故障存储器引起的错误标记的损坏引起的错误 在错误的ECC字中。

    Dirty cacheline duplication
    4.
    发明授权
    Dirty cacheline duplication 有权
    脏的缓存线重复

    公开(公告)号：US09229803B2

    公开(公告)日：2016-01-05

    申请号：US13720536

    申请日：2012-12-19

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Gabriel H. Loh ,  Vilas K. Sridharan ,  James M. O'Connor ,  Jaewoong Sim

    IPC: G06F11/10 ,  G06F12/08

    CPC classification number: G06F11/1064 ,  G06F12/0893

    Abstract: A method of managing memory includes installing a first cacheline at a first location in a cache memory and receiving a write request. In response to the write request, the first cacheline is modified in accordance with the write request and marked as dirty. Also in response to the write request, a second cacheline is installed that duplicates the first cacheline, as modified in accordance with the write request, at a second location in the cache memory.

    Abstract translation: 管理存储器的方法包括在高速缓冲存储器中的第一位置安装第一高速缓存线并接收写入请求。 响应于写入请求，第一个缓存线根据写入请求进行修改并标记为脏。 还响应于写入请求，安装第二高速缓存线，该第二高速缓存线在高速缓冲存储器的第二位置处复制根据写入请求修改的第一高速缓存线。

    METHOD AND APPARATUS FOR ENCODING ERRONEOUS DATA IN AN ERROR CORRECTION CODE PROTECTED MEMORY
    5.
    发明申请
    METHOD AND APPARATUS FOR ENCODING ERRONEOUS DATA IN AN ERROR CORRECTION CODE PROTECTED MEMORY 有权
    在错误修正代码保护的存储器中编码错误数据的方法和装置

    公开(公告)号：US20150278016A1

    公开(公告)日：2015-10-01

    申请号：US14230115

    申请日：2014-03-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ross V. La Fetra ,  Vilas K. Sridharan ,  Vydhyanathan Kalyanasundharam ,  Dean A. Liberty ,  Amit P. Apte

    IPC: G06F11/10

    CPC classification number: G06F11/1076 ,  G06F11/10 ,  G11B20/1833 ,  G11C29/52 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0071 ,  H04L2027/0036

    Abstract: A method and device are described for encoding erroneous data in an error correction code (ECC) protected memory. In one embodiment, incoming data including a plurality of data symbols and a data integrity marker is received. At least one extra symbol is used to mark the incoming data as error-free data or erroneous data (i.e., poison) based on the data integrity marker. ECC may be created to protect the data symbols. The ECC may include a plurality of check symbols, a plurality of unused symbols and the at least one extra symbol. In another embodiment, an error marker may be propagated from a single ECC word to all ECC words of data block (e.g., a cache line, a page, and the like) to prevent errors due to corruption of the error marker caused by faulty memory in the erroneous ECC word.

    Abstract translation: 描述了用于对纠错码（ECC）保护存储器中的错误数据进行编码的方法和装置。 在一个实施例中，接收包括多个数据符号和数据完整性标记的输入数据。 使用至少一个额外的符号来将输入数据标记为基于数据完整性标记的无错误数据或错误数据（即毒药）。 可以创建ECC以保护数据符号。 ECC可以包括多个检查符号，多个未使用的符号和至少一个额外的符号。 在另一个实施例中，错误标记可以从单个ECC字传播到数据块的所有ECC字（例如，高速缓存线，页等），以防止由故障存储器引起的错误标记的损坏引起的错误 在错误的ECC字中。

    Platform first error handling
    8.
    发明授权
    Platform first error handling 有权

    公开(公告)号：US11061753B2

    公开(公告)日：2021-07-13

    申请号：US15940693

    申请日：2018-03-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Dean A. Liberty ,  Vilas K. Sridharan ,  Michael T. Clark ,  Jelena Ilic ,  David S. Christie ,  James R. Williamson ,  Cristian Constantinescu

    IPC: G06F11/07 ,  G06F9/48 ,  G06F9/455 ,  G06F9/30

    Abstract: Systems, apparatuses, and methods for implementing a hardware enforcement mechanism to enable platform-specific firmware visibility into an error state ahead of the operating system are disclosed. A system includes at least one or more processor cores, control logic, a plurality of registers, platform-specific firmware, and an operating system (OS). The control logic allows the platform-specific firmware to decide if and when the error state is visible to the OS. In some cases, the platform-specific firmware blocks the OS from accessing the error state. In other cases, the platform-specific firmware allows the OS to access the error state such as when the OS needs to unmap a page. The control logic enables the platform-specific firmware, rather than the OS, to make decisions about the replacement of faulty components in the system.

    MULTI-LEVEL MEMORY HIERARCHY
    9.
    发明申请
    MULTI-LEVEL MEMORY HIERARCHY 审中-公开
    多级记忆分级

    公开(公告)号：US20150293845A1

    公开(公告)日：2015-10-15

    申请号：US14250474

    申请日：2014-04-11

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Lisa R. Hsu ,  James M. O'Connor ,  Vilas K. Sridharan ,  Gabriel H. Loh ,  Nuwan S. Jayasena ,  Bradford M. Beckmann

    IPC: G06F12/08 ,  G06F12/10

    CPC classification number: G06F12/0811 ,  G06F12/1009 ,  G06F2212/283 ,  G06F2212/651

    Abstract: Described is a system and method for a multi-level memory hierarchy. Each level is based on different attributes including, for example, power, capacity, bandwidth, reliability, and volatility. In some embodiments, the different levels of the memory hierarchy may use an on-chip stacked dynamic random access memory, (providing fast, high-bandwidth, low-energy access to data) and an off-chip non-volatile random access memory, (providing low-power, high-capacity storage), in order to provide higher-capacity, lower power, and higher-bandwidth performance. The multi-level memory may present a unified interface to a processor so that specific memory hardware and software implementation details are hidden. The multi-level memory enables the illusion of a single-level memory that satisfies multiple conflicting constraints. A comparator receives a memory address from the processor, processes the address and reads from or writes to the appropriate memory level. In some embodiments, the memory architecture is visible to the software stack to optimize memory utilization.

    Abstract translation: 描述了用于多级存储器层次结构的系统和方法。 每个级别都是基于不同的属性，包括功率，容量，带宽，可靠性和波动性。 在一些实施例中，存储器层级的不同级别可以使用片上堆叠的动态随机存取存储器（提供对数据的快速，高带宽，低能量访问）和片外非易失性随机存取存储器， （提供低功耗，大容量存储），以提供更高容量，更低功耗和更高带宽的性能。 多级存储器可以向处理器呈现统一的接口，从而隐藏特定的存储器硬件和软件实现细节。 多级存储器能够实现满足多个冲突约束的单级存储器的错觉。 比较器从处理器接收存储器地址，处理地址并读取或写入适当的存储器级别。 在一些实施例中，存储器架构对于软件堆栈是可见的以优化存储器利用。

    DETECTING AND CORRECTING HARD ERRORS IN A MEMORY ARRAY
    10.
    发明申请
    DETECTING AND CORRECTING HARD ERRORS IN A MEMORY ARRAY 有权
    检测和校正存储器阵列中的硬错误

    公开(公告)号：US20150100848A1

    公开(公告)日：2015-04-09

    申请号：US14048830

    申请日：2013-10-08

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John Kalamatianos ,  Johnsy Kanjirapallil John ,  Robert Gelinas ,  Vilas K. Sridharan ,  Phillip E. Nevius

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1008 ,  G11C11/41 ,  G11C29/42 ,  G11C29/52 ,  G11C29/78 ,  G11C2029/0409

    Abstract: Hard errors in the memory array can be detected and corrected in real-time using reusable entries in an error status buffer. Data may be rewritten to a portion of a memory array and a register in response to a first error in data read from the portion of the memory array. The rewritten data may then be written from the register to an entry of an error status buffer in response to the rewritten data read from the register differing from the rewritten data read from the portion of the memory array.

    Abstract translation: 可以使用错误状态缓冲区中的可重用条目实时检测和校正存储器阵列中的硬错误。 响应于从存储器阵列的部分读取的数据中的第一个错误，数据可以重写到存储器阵列和寄存器的一部分。 然后可以将重写的数据从寄存器写入错误状态缓冲器的条目，以响应于从寄存器读取的重写数据与从存储器阵列的部分读取的重写数据不同。

Patent Agency Ranking