公开(公告)号：US20150278016A1

公开(公告)日：2015-10-01

申请号：US14230115

申请日：2014-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Ross V. La Fetra ,  Vilas K. Sridharan ,  Vydhyanathan Kalyanasundharam ,  Dean A. Liberty ,  Amit P. Apte

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/10 ,  G11B20/1833 ,  G11C29/52 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0071 ,  H04L2027/0036

Abstract: A method and device are described for encoding erroneous data in an error correction code (ECC) protected memory. In one embodiment, incoming data including a plurality of data symbols and a data integrity marker is received. At least one extra symbol is used to mark the incoming data as error-free data or erroneous data (i.e., poison) based on the data integrity marker. ECC may be created to protect the data symbols. The ECC may include a plurality of check symbols, a plurality of unused symbols and the at least one extra symbol. In another embodiment, an error marker may be propagated from a single ECC word to all ECC words of data block (e.g., a cache line, a page, and the like) to prevent errors due to corruption of the error marker caused by faulty memory in the erroneous ECC word.

Abstract translation: 描述了用于对纠错码（ECC）保护存储器中的错误数据进行编码的方法和装置。 在一个实施例中，接收包括多个数据符号和数据完整性标记的输入数据。 使用至少一个额外的符号来将输入数据标记为基于数据完整性标记的无错误数据或错误数据（即毒药）。 可以创建ECC以保护数据符号。 ECC可以包括多个检查符号，多个未使用的符号和至少一个额外的符号。 在另一个实施例中，错误标记可以从单个ECC字传播到数据块的所有ECC字（例如，高速缓存线，页等），以防止由故障存储器引起的错误标记的损坏引起的错误 在错误的ECC字中。

公开(公告)号：US09354970B2

公开(公告)日：2016-05-31

申请号：US14230115

申请日：2014-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Ross V. La Fetra ,  Vilas K. Sridharan ,  Vydhyanathan Kalyanasundharam ,  Dean A. Liberty ,  Amit P. Apte

IPC: G06F11/10 ,  H04L1/00 ,  H04L27/00 ,  G11B20/18 ,  G11C29/52

CPC classification number: G06F11/1076 ,  G06F11/10 ,  G11B20/1833 ,  G11C29/52 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0071 ,  H04L2027/0036

Abstract: A method and device are described for encoding erroneous data in an error correction code (ECC) protected memory. In one embodiment, incoming data including a plurality of data symbols and a data integrity marker is received. At least one extra symbol is used to mark the incoming data as error-free data or erroneous data (i.e., poison) based on the data integrity marker. ECC may be created to protect the data symbols. The ECC may include a plurality of check symbols, a plurality of unused symbols and the at least one extra symbol. In another embodiment, an error marker may be propagated from a single ECC word to all ECC words of data block (e.g., a cache line, a page, and the like) to prevent errors due to corruption of the error marker caused by faulty memory in the erroneous ECC word.

Abstract translation: 描述了用于对纠错码（ECC）保护存储器中的错误数据进行编码的方法和装置。 在一个实施例中，接收包括多个数据符号和数据完整性标记的输入数据。 使用至少一个额外的符号来将输入数据标记为基于数据完整性标记的无错误数据或错误数据（即毒药）。 可以创建ECC以保护数据符号。 ECC可以包括多个检查符号，多个未使用的符号和至少一个额外的符号。 在另一个实施例中，错误标记可以从单个ECC字传播到数据块的所有ECC字（例如，高速缓存线，页等），以防止由故障存储器引起的错误标记的损坏引起的错误 在错误的ECC字中。

公开(公告)号：US12072756B2

公开(公告)日：2024-08-27

申请号：US17854710

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Vilas K. Sridharan ,  Dean A. Liberty ,  Magiting Talisayon ,  Srikanth Masanam

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/14 ,  G06F12/02

CPC classification number: G06F11/0772 ,  G06F11/0787 ,  G06F11/1405 ,  G06F12/0292

Abstract: An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). When a host processor in the first partition detects an error that requires information from processor cores of the second partition, the host processor generates an access request with a target address pointing to a storage location in a memory of the second partition, not the first partition. When the host processor receives the requested error log information from the second partition, the host processor completes processing of the error. To support the host processor in generating the target address for the access request, during an earlier bootup operation, the second partition communicates the hardware topology of the second partition to the host processor.

公开(公告)号：US11061753B2

公开(公告)日：2021-07-13

申请号：US15940693

申请日：2018-03-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Dean A. Liberty ,  Vilas K. Sridharan ,  Michael T. Clark ,  Jelena Ilic ,  David S. Christie ,  James R. Williamson ,  Cristian Constantinescu

IPC: G06F11/07 ,  G06F9/48 ,  G06F9/455 ,  G06F9/30

Abstract: Systems, apparatuses, and methods for implementing a hardware enforcement mechanism to enable platform-specific firmware visibility into an error state ahead of the operating system are disclosed. A system includes at least one or more processor cores, control logic, a plurality of registers, platform-specific firmware, and an operating system (OS). The control logic allows the platform-specific firmware to decide if and when the error state is visible to the OS. In some cases, the platform-specific firmware blocks the OS from accessing the error state. In other cases, the platform-specific firmware allows the OS to access the error state such as when the OS needs to unmap a page. The control logic enables the platform-specific firmware, rather than the OS, to make decisions about the replacement of faulty components in the system.

公开(公告)号：US20140156975A1

公开(公告)日：2014-06-05

申请号：US13690841

申请日：2012-11-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Vilas SRIDHARAN ,  James M. O'Connor ,  Steven K. Reinhardt ,  Nuwan S. Jayasena ,  Michael J. Schulte ,  Dean A. Liberty

IPC: G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/3851 ,  G06F9/3887 ,  G06F11/1641 ,  G06F11/1691 ,  G06F11/1695

Abstract: In some embodiments, a method for improving reliability in a processor is provided. The method can include replicating input data for first and second lanes of a processor, the first and second lanes being located in a same cluster of the processor and the first and second lanes each generating a respective value associated with an instruction to be executed in the respective lane, and responsive to a determination that the generated values do not match, providing an indication that the generated values do not match.

Abstract translation: 在一些实施例中，提供了一种用于提高处理器中的可靠性的方法。 该方法可以包括为处理器的第一和第二通道复制输入数据，第一和第二通道位于处理器的相同簇中，并且第一和第二通道各自产生与将要执行的指令相关联的相应值 并且响应于确定所生成的值不匹配，提供所生成的值不匹配的指示。

公开(公告)号：US12111719B2

公开(公告)日：2024-10-08

申请号：US17854788

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Vilas K. Sridharan ,  Magiting Talisayon ,  Srikanth Masanam ,  Dean A. Liberty

IPC: G06F11/07

CPC classification number: G06F11/0787 ,  G06F11/0709 ,  G06F11/0721

Abstract: An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). The first partition includes a host processor that executes an exception handler for managing reported errors. A message converter unit of the second partition assists in generating messages based on detected errors in the second partition. The message converter unit receives requests from hardware components of the second partition for handling errors and translates MCA addresses between the first partition and the second partition. To support the message converter unit, during an earlier bootup operation, the second partition communicates the hardware topology of the second partition to the host processor, and the host processor sends address translation information.

公开(公告)号：US20240004750A1

公开(公告)日：2024-01-04

申请号：US17854788

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Vilas K. Sridharan ,  Magiting Talisayon ,  Srikanth Masanam ,  Dean A. Liberty

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0709 ,  G06F11/0721

Abstract: An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). The first partition includes a host processor that executes an exception handler for managing reported errors. A message converter unit of the second partition assists in generating messages based on detected errors in the second partition. The message converter unit receives requests from hardware components of the second partition for handling errors and translates MCA addresses between the first partition and the second partition. To support the message converter unit, during an earlier bootup operation, the second partition communicates the hardware topology of the second partition to the host processor, and the host processor sends address translation information.

公开(公告)号：US20240004744A1

公开(公告)日：2024-01-04

申请号：US17854710

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Vilas K. Sridharan ,  Dean A. Liberty ,  Magiting Talisayon ,  Srikanth Masanam

IPC: G06F11/07 ,  G06F11/14 ,  G06F12/02

CPC classification number: G06F11/0772 ,  G06F11/0787 ,  G06F11/1405 ,  G06F12/0292

Abstract: An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). When a host processor in the first partition detects an error that requires information from processor cores of the second partition, the host processor generates an access request with a target address pointing to a storage location in a memory of the second partition, not the first partition. When the host processor receives the requested error log information from the second partition, the host processor completes processing of the error. To support the host processor in generating the target address for the access request, during an earlier bootup operation, the second partition communicates the hardware topology of the second partition to the host processor.

公开(公告)号：US20190303230A1

公开(公告)日：2019-10-03

申请号：US15940693

申请日：2018-03-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Dean A. Liberty ,  Vilas K. Sridharan ,  Michael T. Clark ,  Jelena Ilic ,  David S. Christie ,  James R. Williamson ,  Cristian Constantinescu

IPC: G06F11/07 ,  G06F9/48 ,  G06F9/30 ,  G06F9/455

Abstract: Systems, apparatuses, and methods for implementing a hardware enforcement mechanism to enable platform-specific firmware visibility into an error state ahead of the operating system are disclosed. A system includes at least one or more processor cores, control logic, a plurality of registers, platform-specific firmware, and an operating system (OS). The control logic allows the platform-specific firmware to decide if and when the error state is visible to the OS. In some cases, the platform-specific firmware blocks the OS from accessing the error state. In other cases, the platform-specific firmware allows the OS to access the error state such as when the OS needs to unmap a page. The control logic enables the platform-specific firmware, rather than the OS, to make decisions about the replacement of faulty components in the system.