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公开(公告)号：US12056522B2
公开(公告)日：2024-08-06
申请号：US17530936
申请日：2021-11-19
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Michael L. Golden , Paul Blinzer , Magiting M. Talisayon , Srikanth Masanam , Ripal Butani , Upasanah Swaminathan
CPC classification number: G06F9/4881 , G06F2209/482
Abstract: Within a processing system, thread count asymmetries manifest when one or more cores of a processing device are disabled. To determine such thread count asymmetries, discovery operations are performed to determine thread count asymmetries for one or more hierarchy levels of a processing device based on a number of threads per enumerated instance within the hierarchy level. In response to the determining a thread count asymmetry, one thread identifier for each enumerated instance within the asymmetric hierarchy level is defined to determine a representation of the asymmetry. Using the representation of the symmetry, software tasks associated with one or more application within the processing system are performed.
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公开(公告)号：US20230161618A1
公开(公告)日：2023-05-25
申请号：US17530936
申请日：2021-11-19
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Michael L. Golden , Paul Blinzer , Magiting M. Talisayon , Srikanth Masanam , Ripal Butani , Upasanah Swaminathan
IPC: G06F9/48
CPC classification number: G06F9/4881 , G06F2209/482
Abstract: Within a processing system, thread count asymmetries manifest when one or more cores of a processing device are disabled. To determine such thread count asymmetries, discovery operations are performed to determine thread count asymmetries for one or more hierarchy levels of a processing device based on a number of threads per enumerated instance within the hierarchy level. In response to the determining a thread count asymmetry, one thread identifier for each enumerated instance within the asymmetric hierarchy level is defined to determine a representation of the asymmetry. Using the representation of the symmetry, software tasks associated with one or more application within the processing system are performed.
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Patent Agency Ranking
公开(公告)号：US20250021379A1
公开(公告)日：2025-01-16
申请号：US18780862
申请日：2024-07-23
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Michael L. Golden , Paul Blinzer , Magiting M. Talisayon , Srikanth Masanam , Ripal Butani , Upasanah Swaminathan
IPC: G06F9/48
Abstract: Within a processing system, thread count asymmetries manifest when one or more cores of a processing device are disabled. To determine such thread count asymmetries, discovery operations are performed to determine thread count asymmetries for one or more hierarchy levels of a processing device based on a number of threads per enumerated instance within the hierarchy level. In response to the determining a thread count asymmetry, one thread identifier for each enumerated instance within the asymmetric hierarchy level is defined to determine a representation of the asymmetry. Using the representation of the symmetry, software tasks associated with one or more application within the processing system are performed.
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公开(公告)号：US12072756B2
公开(公告)日：2024-08-27
申请号：US17854710
申请日：2022-06-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Vilas K. Sridharan , Dean A. Liberty , Magiting Talisayon , Srikanth Masanam
CPC classification number: G06F11/0772 , G06F11/0787 , G06F11/1405 , G06F12/0292
Abstract: An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). When a host processor in the first partition detects an error that requires information from processor cores of the second partition, the host processor generates an access request with a target address pointing to a storage location in a memory of the second partition, not the first partition. When the host processor receives the requested error log information from the second partition, the host processor completes processing of the error. To support the host processor in generating the target address for the access request, during an earlier bootup operation, the second partition communicates the hardware topology of the second partition to the host processor.
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公开(公告)号：US12111719B2
公开(公告)日：2024-10-08
申请号：US17854788
申请日：2022-06-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Vilas K. Sridharan , Magiting Talisayon , Srikanth Masanam , Dean A. Liberty
IPC: G06F11/07
CPC classification number: G06F11/0787 , G06F11/0709 , G06F11/0721
Abstract: An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). The first partition includes a host processor that executes an exception handler for managing reported errors. A message converter unit of the second partition assists in generating messages based on detected errors in the second partition. The message converter unit receives requests from hardware components of the second partition for handling errors and translates MCA addresses between the first partition and the second partition. To support the message converter unit, during an earlier bootup operation, the second partition communicates the hardware topology of the second partition to the host processor, and the host processor sends address translation information.
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公开(公告)号：US20240004750A1
公开(公告)日：2024-01-04
申请号：US17854788
申请日：2022-06-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Vilas K. Sridharan , Magiting Talisayon , Srikanth Masanam , Dean A. Liberty
IPC: G06F11/07
CPC classification number: G06F11/0793 , G06F11/0709 , G06F11/0721
Abstract: An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). The first partition includes a host processor that executes an exception handler for managing reported errors. A message converter unit of the second partition assists in generating messages based on detected errors in the second partition. The message converter unit receives requests from hardware components of the second partition for handling errors and translates MCA addresses between the first partition and the second partition. To support the message converter unit, during an earlier bootup operation, the second partition communicates the hardware topology of the second partition to the host processor, and the host processor sends address translation information.
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公开(公告)号：US20240004744A1
公开(公告)日：2024-01-04
申请号：US17854710
申请日：2022-06-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Vilas K. Sridharan , Dean A. Liberty , Magiting Talisayon , Srikanth Masanam
CPC classification number: G06F11/0772 , G06F11/0787 , G06F11/1405 , G06F12/0292
Abstract: An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). When a host processor in the first partition detects an error that requires information from processor cores of the second partition, the host processor generates an access request with a target address pointing to a storage location in a memory of the second partition, not the first partition. When the host processor receives the requested error log information from the second partition, the host processor completes processing of the error. To support the host processor in generating the target address for the access request, during an earlier bootup operation, the second partition communicates the hardware topology of the second partition to the host processor.
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