公开(公告)号：US20230032375A1

公开(公告)日：2023-02-02

申请号：US17390293

申请日：2021-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric Busta ,  Michael L. Golden ,  Sean M. O'Mullan ,  James Wingfield ,  Keith A. Kasprak ,  Russell Schreiber ,  Michael Estlick

IPC: G06F11/14 ,  G06F11/07 ,  G06F9/30 ,  G06F9/50

Abstract: An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of undefective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.

公开(公告)号：US11704248B2

公开(公告)日：2023-07-18

申请号：US17091993

申请日：2020-11-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： William L. Walker ,  Michael L. Golden ,  Marius Evers

IPC: G06F12/0862 ,  G06F12/128 ,  G06F12/1027 ,  G06F1/3234 ,  G06F12/0815 ,  G06F12/1009 ,  G06F12/0811

CPC classification number: G06F12/0862 ,  G06F1/3275 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/128 ,  G06F2212/602 ,  G06F2212/65 ,  G06F2212/68

Abstract: A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.

公开(公告)号：US20220413584A1

公开(公告)日：2022-12-29

申请号：US17358709

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard Martin Born ,  Gokul Subramani Ramalingam Lakshmi Devi ,  Michael L. Golden ,  Larry D. Hewitt

IPC: G06F1/3228

Abstract: Methods and systems for facilitating improved power consumption control of a plurality of processing cores are disclosed. The methods improve the power consumption control by performing power throttling based on a determined excess power consumption. The methods include the steps of: monitoring using at least one event count component in the respective processing core a plurality of distributed events; calculating an accumulated weighted sum of the distributed events from the event count component; determining an excess power consumption by comparing the accumulated weighted sum with a threshold power value; and adjusting power consumption of the respective processing core based on the determined excess power consumption.

公开(公告)号：US11460879B1

公开(公告)日：2022-10-04

申请号：US17358622

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Amitabh Mehra ,  Richard Martin Born ,  Sriram Srinivasan ,  Sneha Komatireddy ,  Michael L. Golden ,  Xiuting Kaleen C. Man ,  Gokul Subramani Ramalingam Lakshmi Devi ,  Xiaojie He

IPC: G06F1/10 ,  G06F1/3206

Abstract: Methods and apparatuses control electrical current supplied to a plurality of processing units in a multi-processor system. A plurality of current usage information corresponding to the processing units are received by a controller to determine a threshold current for each of the processing units. The controller determines a frequency reduction action and an instructions-per-cycle (IPC) reduction action for the each of the processing units based on the threshold current and regulates operations of the processing units based on the determined frequency and IPC reduction actions.

公开(公告)号：US20250021379A1

公开(公告)日：2025-01-16

申请号：US18780862

申请日：2024-07-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael L. Golden ,  Paul Blinzer ,  Magiting M. Talisayon ,  Srikanth Masanam ,  Ripal Butani ,  Upasanah Swaminathan

IPC: G06F9/48

Abstract: Within a processing system, thread count asymmetries manifest when one or more cores of a processing device are disabled. To determine such thread count asymmetries, discovery operations are performed to determine thread count asymmetries for one or more hierarchy levels of a processing device based on a number of threads per enumerated instance within the hierarchy level. In response to the determining a thread count asymmetry, one thread identifier for each enumerated instance within the asymmetric hierarchy level is defined to determine a representation of the asymmetry. Using the representation of the symmetry, software tasks associated with one or more application within the processing system are performed.

公开(公告)号：US11907070B2

公开(公告)日：2024-02-20

申请号：US17390293

申请日：2021-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric Busta ,  Michael L. Golden ,  Sean M. O′Mullan ,  James Wingfield ,  Keith A. Kasprak ,  Russell Schreiber ,  Michael Estlick

IPC: G06F11/14 ,  G06F9/30 ,  G06F9/50 ,  G06F11/07

CPC classification number: G06F11/1417 ,  G06F9/3013 ,  G06F9/5011 ,  G06F11/0772

Abstract: An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of defective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.

公开(公告)号：US10956332B2

公开(公告)日：2021-03-23

申请号：US15800727

申请日：2017-11-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： William L. Walker ,  Michael L. Golden ,  Marius Evers

IPC: G06F12/0862 ,  G06F12/128 ,  G06F12/1027 ,  G06F1/3234 ,  G06F12/0815 ,  G06F12/1009 ,  G06F12/0811

Abstract: A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.

公开(公告)号：US12056522B2

公开(公告)日：2024-08-06

申请号：US17530936

申请日：2021-11-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael L. Golden ,  Paul Blinzer ,  Magiting M. Talisayon ,  Srikanth Masanam ,  Ripal Butani ,  Upasanah Swaminathan

IPC: G06F9/44 ,  G06F9/48

CPC classification number: G06F9/4881 ,  G06F2209/482

Abstract: Within a processing system, thread count asymmetries manifest when one or more cores of a processing device are disabled. To determine such thread count asymmetries, discovery operations are performed to determine thread count asymmetries for one or more hierarchy levels of a processing device based on a number of threads per enumerated instance within the hierarchy level. In response to the determining a thread count asymmetry, one thread identifier for each enumerated instance within the asymmetric hierarchy level is defined to determine a representation of the asymmetry. Using the representation of the symmetry, software tasks associated with one or more application within the processing system are performed.

公开(公告)号：US20230161618A1

公开(公告)日：2023-05-25

申请号：US17530936

申请日：2021-11-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael L. Golden ,  Paul Blinzer ,  Magiting M. Talisayon ,  Srikanth Masanam ,  Ripal Butani ,  Upasanah Swaminathan

IPC: G06F9/48

CPC classification number: G06F9/4881 ,  G06F2209/482

Abstract: Within a processing system, thread count asymmetries manifest when one or more cores of a processing device are disabled. To determine such thread count asymmetries, discovery operations are performed to determine thread count asymmetries for one or more hierarchy levels of a processing device based on a number of threads per enumerated instance within the hierarchy level. In response to the determining a thread count asymmetry, one thread identifier for each enumerated instance within the asymmetric hierarchy level is defined to determine a representation of the asymmetry. Using the representation of the symmetry, software tasks associated with one or more application within the processing system are performed.