公开(公告)号：US20240202116A1

公开(公告)日：2024-06-20

申请号：US18068930

申请日：2022-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  John Kalamatianos ,  Paul James Moyer ,  Nicholas Dean Lance ,  Sriram Srinivasan ,  Patrick James Shyvers ,  William Louie Walker

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/1044

Abstract: An entry of a last level cache shadow tag array to track pending last level cache misses to private data in a previous level cache (e.g., an L2 cache), that also are misses to an exclusive last level cache (e.g., an L3 cache) and to the last level cache shadow tag array. Accordingly, last level cache miss status holding registers need not be expended to track cache misses to private data that are already being tracked by a previous level cache miss status holding register. Additionally or alternatively, up to a threshold number of last level cache pending misses to the same shared data from different processor cores are tracked in the last level cache shadow tag array, and any additional last level cache pending misses are tracked in a last level cache miss status holding register.

公开(公告)号：US11275688B2

公开(公告)日：2022-03-15

申请号：US16700671

申请日：2019-12-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sriram Srinivasan ,  John Kelley ,  Matthew Schoenwald

IPC: G06F12/084

Abstract: A processing system includes a plurality of compute units, with each compute unit having an associated first cache of a plurality of first caches, and a second cache shared by the plurality of compute units. The second cache operates to manage transfers of caches between the first caches of the plurality of first caches such that when multiple candidate first caches contain a valid copy of a requested cacheline, the second cache selects the candidate first cache having the shortest total path from the second cache to the candidate first cache and from the candidate first cache to the compute unit issuing a request for the requested cacheline.

公开(公告)号：US20170357585A1

公开(公告)日：2017-12-14

申请号：US15180828

申请日：2016-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul James Moyer ,  William Louie Walker ,  Sriram Srinivasan

IPC: G06F12/0811 ,  G06F12/0842 ,  G06F12/0862 ,  G06F12/084 ,  G06F12/12

CPC classification number: G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0862 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/1024 ,  G06F2212/602 ,  G06F2212/6042

Abstract: A processor replaces data at a first cache based on hints from a second cache, wherein the hints indicate information about the data that is not available to the first cache directly. When data at an entry is transferred from the first cache to the second cache, the first cache can provide an age hint to the second cache to indicate that the data should be assigned a higher or lower initial age relative to a nominal initial age. The second cache assigns the entry for the data an initial age based on the age hint and, when replacing data, selects data for replacement based on the age of each entry.

公开(公告)号：US20140317356A1

公开(公告)日：2014-10-23

申请号：US13864542

申请日：2013-04-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sriram Srinivasan ,  Tarun Nakra

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0844 ,  G06F12/0857 ,  Y02D10/13

Abstract: A processor includes a processing unit, a cache memory, and a central request queue. The central request queue is operable to receive a prefetch load request for a cache line to be loaded into the cache memory, receive a demand load request for the cache line from the processing unit, merge the prefetch load request and the demand load request to generate a promoted load request specifying the processing unit as a requestor, receive the cache line associated with the promoted load request, and forward the cache line to the processing unit.

Abstract translation: 处理器包括处理单元，高速缓冲存储器和中央请求队列。 中央请求队列可操作以接收用于要加载到高速缓存存储器中的高速缓存行的预取加载请求，从处理单元接收对高速缓存行的请求加载请求，合并预取加载请求和请求加载请求以生成 指定处理单元作为请求者的升级加载请求，接收与所提升的加载请求相关联的高速缓存行，并将高速缓存行转发到处理单元。

公开(公告)号：US10073776B2

公开(公告)日：2018-09-11

申请号：US15190607

申请日：2016-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Sriram Srinivasan ,  William L. Walker

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0842

CPC classification number: G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F2212/1016 ,  G06F2212/6042

Abstract: A processing system includes a plurality of processor cores and a plurality of private caches. Each private cache is associated with a corresponding processor core of the plurality of processor cores and includes a corresponding first set of cachelines. The processing system further includes a shared cache shared by the plurality of processor cores. The shared cache includes a second set of cachelines, and a shadow tag memory including a plurality of entries, each entry storing state information for a corresponding cacheline of the first set of cachelines of one of the private caches.

公开(公告)号：US20170371786A1

公开(公告)日：2017-12-28

申请号：US15190607

申请日：2016-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Sriram Srinivasan ,  William L. Walker

IPC: G06F12/0811 ,  G06F12/084 ,  G06F12/0815 ,  G06F12/0842

CPC classification number: G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F2212/1016 ,  G06F2212/6042

Abstract: A processing system includes a plurality of processor cores and a plurality of private caches. Each private cache is associated with a corresponding processor core of the plurality of processor cores and includes a corresponding first set of cachelines. The processing system further includes a shared cache shared by the plurality of processor cores. The shared cache includes a second set of cachelines, and a shadow tag memory including a plurality of entries, each entry storing state information for a corresponding cacheline of the first set of cachelines of one of the private caches.

公开(公告)号：US11928060B2

公开(公告)日：2024-03-12

申请号：US17666950

申请日：2022-02-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sriram Srinivasan ,  John Kelley ,  Matthew Schoenwald

IPC: G06F12/084

CPC classification number: G06F12/084 ,  G06F2212/1021 ,  G06F2212/1041

Abstract: A processing system includes a plurality of compute units, with each compute unit having an associated first cache of a plurality of first caches, and a second cache shared by the plurality of compute units. The second cache operates to manage transfers of caches between the first caches of the plurality of first caches such that when multiple candidate first caches contain a valid copy of a requested cacheline, the second cache selects the candidate first cache having the shortest total path from the second cache to the candidate first cache and from the candidate first cache to the compute unit issuing a request for the requested cacheline.

公开(公告)号：US11853111B2

公开(公告)日：2023-12-26

申请号：US17940490

申请日：2022-09-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Amitabh Mehra ,  Richard Martin Born ,  Sriram Srinivasan ,  Sneha Komatireddy ,  Michael L Golden ,  Xiuting Kaleen C. Man ,  Gokul Subramani Ramalingam Lakshmi Devi ,  Xiaojie He

IPC: G06F1/10 ,  G06F1/3206

CPC classification number: G06F1/10 ,  G06F1/3206

Abstract: Methods and apparatuses control electrical current supplied to a plurality of processing units in a multi-processor system. A plurality of current usage information corresponding to the processing units are received by a controller to determine a threshold current for each of the processing units. The controller determines a frequency reduction action and an instructions-per-cycle (IPC) reduction action for the each of the processing units based on the threshold current and regulates operations of the processing units based on the determined frequency and IPC reduction actions.

公开(公告)号：US11460879B1

公开(公告)日：2022-10-04

申请号：US17358622

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Amitabh Mehra ,  Richard Martin Born ,  Sriram Srinivasan ,  Sneha Komatireddy ,  Michael L. Golden ,  Xiuting Kaleen C. Man ,  Gokul Subramani Ramalingam Lakshmi Devi ,  Xiaojie He

IPC: G06F1/10 ,  G06F1/3206

Abstract: Methods and apparatuses control electrical current supplied to a plurality of processing units in a multi-processor system. A plurality of current usage information corresponding to the processing units are received by a controller to determine a threshold current for each of the processing units. The controller determines a frequency reduction action and an instructions-per-cycle (IPC) reduction action for the each of the processing units based on the threshold current and regulates operations of the processing units based on the determined frequency and IPC reduction actions.

公开(公告)号：US09286223B2

公开(公告)日：2016-03-15

申请号：US13864542

申请日：2013-04-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sriram Srinivasan ,  Tarun Nakra

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0844 ,  G06F12/0857 ,  Y02D10/13

Abstract: A processor includes a processing unit, a cache memory, and a central request queue. The central request queue is operable to receive a prefetch load request for a cache line to be loaded into the cache memory, receive a demand load request for the cache line from the processing unit, merge the prefetch load request and the demand load request to generate a promoted load request specifying the processing unit as a requestor, receive the cache line associated with the promoted load request, and forward the cache line to the processing unit.

Abstract translation: 处理器包括处理单元，高速缓冲存储器和中央请求队列。 中央请求队列可操作以接收用于要加载到高速缓存存储器中的高速缓存行的预取加载请求，从处理单元接收对高速缓存行的请求加载请求，合并预取加载请求和请求加载请求以生成 指定处理单元作为请求者的升级加载请求，接收与所提升的加载请求相关联的高速缓存行，并将高速缓存行转发到处理单元。