公开(公告)号：US11977890B2

公开(公告)日：2024-05-07

申请号：US17566040

申请日：2021-12-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Magiting M. Talisayon ,  Luca Schiano ,  Neil N. Marketkar ,  Yueh-Chuan Tzeng

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30149 ,  G06F9/30058 ,  G06F9/30065 ,  G06F9/3836 ,  G06F9/3861

Abstract: Stateful microbranch instructions, including: generating, based on an instruction, a first one or more microinstructions including a stateful microbranch instruction, wherein the stateful microbranch instruction includes: an address of a next instruction after the instruction; a branch target address; one or more microcode attributes; and executing the first one or more microinstructions.

公开(公告)号：US12056522B2

公开(公告)日：2024-08-06

申请号：US17530936

申请日：2021-11-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael L. Golden ,  Paul Blinzer ,  Magiting M. Talisayon ,  Srikanth Masanam ,  Ripal Butani ,  Upasanah Swaminathan

IPC: G06F9/44 ,  G06F9/48

CPC classification number: G06F9/4881 ,  G06F2209/482

Abstract: Within a processing system, thread count asymmetries manifest when one or more cores of a processing device are disabled. To determine such thread count asymmetries, discovery operations are performed to determine thread count asymmetries for one or more hierarchy levels of a processing device based on a number of threads per enumerated instance within the hierarchy level. In response to the determining a thread count asymmetry, one thread identifier for each enumerated instance within the asymmetric hierarchy level is defined to determine a representation of the asymmetry. Using the representation of the symmetry, software tasks associated with one or more application within the processing system are performed.

公开(公告)号：US20230161618A1

公开(公告)日：2023-05-25

申请号：US17530936

申请日：2021-11-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael L. Golden ,  Paul Blinzer ,  Magiting M. Talisayon ,  Srikanth Masanam ,  Ripal Butani ,  Upasanah Swaminathan

IPC: G06F9/48

CPC classification number: G06F9/4881 ,  G06F2209/482

Abstract: Within a processing system, thread count asymmetries manifest when one or more cores of a processing device are disabled. To determine such thread count asymmetries, discovery operations are performed to determine thread count asymmetries for one or more hierarchy levels of a processing device based on a number of threads per enumerated instance within the hierarchy level. In response to the determining a thread count asymmetry, one thread identifier for each enumerated instance within the asymmetric hierarchy level is defined to determine a representation of the asymmetry. Using the representation of the symmetry, software tasks associated with one or more application within the processing system are performed.

公开(公告)号：US20250021379A1

公开(公告)日：2025-01-16

申请号：US18780862

申请日：2024-07-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael L. Golden ,  Paul Blinzer ,  Magiting M. Talisayon ,  Srikanth Masanam ,  Ripal Butani ,  Upasanah Swaminathan

IPC: G06F9/48

Abstract: Within a processing system, thread count asymmetries manifest when one or more cores of a processing device are disabled. To determine such thread count asymmetries, discovery operations are performed to determine thread count asymmetries for one or more hierarchy levels of a processing device based on a number of threads per enumerated instance within the hierarchy level. In response to the determining a thread count asymmetry, one thread identifier for each enumerated instance within the asymmetric hierarchy level is defined to determine a representation of the asymmetry. Using the representation of the symmetry, software tasks associated with one or more application within the processing system are performed.