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    SYSTEMS AND METHODS FOR IMPROVING RESOURCE UTILIZATION AND SYSTEM PERFORMANCE IN END-TO-END ENCRYPTION
    1.
    发明公开
    SYSTEMS AND METHODS FOR IMPROVING RESOURCE UTILIZATION AND SYSTEM PERFORMANCE IN END-TO-END ENCRYPTION 审中-公开

    公开(公告)号：US20240333519A1

    公开(公告)日：2024-10-03

    申请号：US18194394

    申请日：2023-03-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： SeyedMohammad SeyedzadehDelcheh ,  Sergey Blagodurov ,  Donald Matthews, Jr. ,  Srilatha Manne

    IPC: H04L9/32

    CPC classification number: H04L9/3242

    Abstract: The disclosed computing device can include super flow control unit (flit) generation circuitry configured to generate a super flit containing two or more flits having two or more requests embedded therein, wherein the two or more requests have the same destination node identifiers and the super flit has a variable size based on a flit size and a number of existing requests in a source node that target a same destination node. The device can additionally include authentication circuitry configured to append a message authentication code to a last flit of the super flit. The device can also include communication circuitry configured to send the super flit to a network switch configured to route the super flit to a destination node corresponding to the same destination node identifiers. Various other methods, systems, and computer-readable media are also disclosed.

    Method and system for shutting down active core based caches
    2.
    发明授权
    Method and system for shutting down active core based caches 有权
    关闭基于活动核心的缓存的方法和系统

    公开(公告)号：US09372803B2

    公开(公告)日：2016-06-21

    申请号：US13722808

    申请日：2012-12-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Srilatha Manne ,  Michael Schulte ,  Lloyd Bircher ,  Madhu Saravana Sibi Govindan ,  Yasuko Eckert

    IPC: G06F12/08

    CPC classification number: G06F12/0891 ,  G06F12/0806 ,  G06F2212/1028 ,  Y02D10/13

    Abstract: A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.

    Abstract translation: 提出了一种系统和方法。 一些实施例包括处理单元，耦合到处理单元的至少一个存储器以及耦合到处理单元并被分成一系列块的至少一个高速缓存，其中该系列高速缓存块中的至少一个包括被识别为 处于修改状态。 通过基于回写策略将数据写入至少一个存储器来刷新修改的状态数据，并且策略的侵略性基于至少一个因素，包括空闲核心数量，最后一个高速缓存刷新的接近度， 与数据相关联的线程的活动，以及哪些核心是空闲的，以及空闲核心是否与数据相关联。

    Using predictions for store-to-load forwarding
    3.
    发明授权
    Using predictions for store-to-load forwarding 有权
    使用商店到装载转发的预测

    公开(公告)号：US09367455B2

    公开(公告)日：2016-06-14

    申请号：US14018562

    申请日：2013-09-05

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Yasuko Eckert ,  Lena E. Olson ,  Srilatha Manne ,  James M. O'Connor

    IPC: G06F9/30 ,  G06F12/08 ,  G06F12/12

    CPC classification number: G06F12/0802 ,  G06F9/3834 ,  G06F9/3838 ,  G06F12/0848 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/123 ,  G06F2212/1016 ,  G06F2212/451 ,  G06F2212/502 ,  G06F2212/6022 ,  G06F2212/6032 ,  Y02D10/13

    Abstract: The described embodiments include a core that uses predictions for store-to-load forwarding. In the described embodiments, the core comprises a load-store unit, a store buffer, and a prediction mechanism. During operation, the prediction mechanism generates a prediction that a load will be satisfied using data forwarded from the store buffer because the load loads data from a memory location in a stack. Based on the prediction, the load-store unit first sends a request for the data to the store buffer in an attempt to satisfy the load using data forwarded from the store buffer. If data is returned from the store buffer, the load is satisfied using the data. However, if the attempt to satisfy the load using data forwarded from the store buffer is unsuccessful, the load-store unit then separately sends a request for the data to a cache to satisfy the load.

    Abstract translation: 所描述的实施例包括使用对存储到负载转发的预测的核心。 在所描述的实施例中，核心包括加载存储单元，存储缓冲器和预测机制。 在运行期间，预测机制产生一个预测，即使用从存储缓冲器转发的数据来满足负载，因为负载从栈中的存储器位置加载数据。 基于该预测，加载存储单元首先向存储缓冲器发送对数据的请求，以尝试使用从存储缓冲器转发的数据来满足负载。 如果从存储缓冲区返回数据，则使用该数据来满足负载。 然而，如果使用从存储缓冲器转发的数据来满足负载的尝试不成功，则加载存储单元然后分别向缓存发送用于满足负载的数据请求。

    Mechanisms to bound the presence of cache blocks with specific properties in caches
    4.
    发明授权
    Mechanisms to bound the presence of cache blocks with specific properties in caches 有权
    限制缓存中具有特定属性的高速缓存块的存在的机制

    公开(公告)号：US09251069B2

    公开(公告)日：2016-02-02

    申请号：US14055869

    申请日：2013-10-16

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Yasuko Eckert ,  Gabriel H. Loh ,  Mauricio Breternitz ,  James M. O'Connor ,  Srilatha Manne ,  Nuwan S. Jayasena ,  Mithuna S. Thottethodi

    IPC: G06F12/08

    CPC classification number: G06F12/0808 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/0848 ,  G06F12/0888 ,  G06F12/0897 ,  Y02D10/13 ,  Y02D10/14

    Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, wherein a first bank is powered down. In response a write request to a second bank for data indicated to be stored in the powered down first bank, the cache controller determines a respective bypass condition for the data. If the bypass condition exceeds a threshold, then the cache controller invalidates any copy of the data stored in the second bank. If the bypass condition does not exceed the threshold, then the cache controller stores the data with a clean state in the second bank. The cache controller writes the data in a lower-level memory for both cases.

    Abstract translation: 一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。 计算系统包括高速缓存阵列和对应的高速缓存控制器。 高速缓存阵列包括多个存储体，其中第一存储体断电。 作为响应，向第二存储体写入请求以指示存储在掉电第一存储体中的数据，高速缓存控制器确定数据的相应旁路条件。 如果旁路条件超过阈值，则高速缓存控制器使存储在第二组中的数据的任何副本无效。 如果旁路条件不超过阈值，则高速缓存控制器将具有干净状态的数据存储在第二存储体中。 高速缓存控制器将这些数据写入较低级别的内存。

    GUARDBAND REDUCTION FOR MULTI-CORE DATA PROCESSOR
    5.
    发明申请
    GUARDBAND REDUCTION FOR MULTI-CORE DATA PROCESSOR 有权
    多核数据处理器的保护减少

    公开(公告)号：US20140181537A1

    公开(公告)日：2014-06-26

    申请号：US13724271

    申请日：2012-12-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Srilatha Manne ,  Rajagopalan Desikan ,  Sanjay Pant ,  Youngtaek Kim

    IPC: G06F1/26

    CPC classification number: G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20

    Abstract: A multi-core data processor includes multiple data processor cores and a power controller. Each data processor core has a first input for receiving a clock signal, a second input for receiving a power supply voltage, and an output for providing an idle signal. The power controller is coupled to each of the data processor cores for providing the clock signal and the power supply voltage to each of the data processor cores. The power controller provides at least one of the clock signal and the power supply voltage to an active one of the data processor cores in dependence on a number of idle signals received from the data processor cores.

    Abstract translation: 多核数据处理器包括多个数据处理器内核和电源控制器。 每个数据处理器内核具有用于接收时钟信号的第一输入端，用于接收电源电压的第二输入端和用于提供空闲信号的输出端。 功率控制器耦合到每个数据处理器核心，用于向每个数据处理器核提供时钟信号和电源电压。 功率控制器根据从数据处理器核心接收到的空闲信号的数量，向时钟信号和电源电压提供至少一个数据处理器核心中的一个。

    METHOD AND SYSTEM FOR SHUTTING DOWN ACTIVE CORE BASED CACHES
    6.
    发明申请
    METHOD AND SYSTEM FOR SHUTTING DOWN ACTIVE CORE BASED CACHES 有权
    用于切换基于活动核心的快照的方法和系统

    公开(公告)号：US20140181413A1

    公开(公告)日：2014-06-26

    申请号：US13722808

    申请日：2012-12-20

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Srilatha Manne ,  Michael Schulte ,  Lloyd Bircher ,  Madhu Saravana Sibi Govindan ,  Yasuko Eckert

    IPC: G06F12/08

    CPC classification number: G06F12/0891 ,  G06F12/0806 ,  G06F2212/1028 ,  Y02D10/13

    Abstract: A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.

    Abstract translation: 提出了一种系统和方法。 一些实施例包括处理单元，耦合到处理单元的至少一个存储器以及耦合到处理单元并被分成一系列块的至少一个高速缓存，其中该系列高速缓存块中的至少一个包括被识别为 处于修改状态。 通过基于回写策略将数据写入至少一个存储器来刷新修改的状态数据，并且策略的侵略性基于至少一个因素，包括空闲核心数量，最后一个高速缓存刷新的接近度， 与数据相关联的线程的活动，以及哪些核心是空闲的，以及空闲核心是否与数据相关联。

    Determining thermal time constants of processing systems
    8.
    发明授权
    Determining thermal time constants of processing systems 有权

    公开(公告)号：US10281964B2

    公开(公告)日：2019-05-07

    申请号：US15010965

    申请日：2016-01-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Can Hankendi ,  Manish Arora ,  Indrain Paul ,  Wei Huang ,  Srilatha Manne

    IPC: G06F1/20 ,  G06F11/30

    Abstract: A processing system includes one or more processing units to perform operations and one or more sensors to measure a temperature concurrently with the one or more processing units performing the operations. The processing system also includes a controller to receive feedback indicating the temperature and to determine a peak temperature and a thermal time constant for heating of the processing system based on a comparison of the measured temperature to a first temperature that is predicted based on the peak temperature and a previously determined thermal time constant for heating. Some embodiments of the controller can control a performance state of the processing system based on the peak temperature and the thermal time constant for heating of the processing system.

    POWER MANAGEMENT ACROSS HETEROGENEOUS PROCESSING UNITS
    10.
    发明申请
    POWER MANAGEMENT ACROSS HETEROGENEOUS PROCESSING UNITS 有权
    电源管理异步加工单元

    公开(公告)号：US20150355692A1

    公开(公告)日：2015-12-10

    申请号：US14297208

    申请日：2014-06-05

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Indrani Paul ,  Vignesh Trichy Ravi ,  Manish Arora ,  Srilatha Manne

    IPC: G06F1/20 ,  G06F9/50 ,  G06F11/30 ,  G06F1/32

    CPC classification number: G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F9/5094 ,  G06F11/3058 ,  G06F11/3409 ,  G06F11/3447 ,  Y02D10/126 ,  Y02D10/22

    Abstract: A method includes controlling active frequency states of a plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. A processor includes a plurality of heterogeneous processing units and a performance controller to control active frequency states of the plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. The active frequency state of a first type of processing unit in the plurality of heterogeneous processing units is controlled based on a first activity metric associated with a first type of processing unit and a second activity metric associated with a second type of processing unit.

    Abstract translation: 一种方法包括基于指示多个异构处理单元中的不同类型的处理单元之间的性能耦合的频率灵敏度度量来控制多个异构处理单元的活动频率状态。 处理器包括多个异构处理单元和性能控制器，用于基于指示多个异构处理单元中的不同类型的处理单元之间的性能耦合的频率灵敏度度量来控制多个异构处理单元的有效频率状态。 基于与第一类型处理单元相关联的第一活动度量和与第二类型处理单元相关联的第二活动度量来控制多个异构处理单元中的第一类型处理单元的活动频率状态。

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