公开(公告)号：US20150363116A1

公开(公告)日：2015-12-17

申请号：US14302964

申请日：2014-06-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Sibi Govindan ,  Sadagopan Srinivasan ,  Lloyd Bircher

IPC: G06F3/06 ,  G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G06F1/3296 ,  G06F11/3037 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/81 ,  G06F2201/88 ,  G06F2201/885 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D10/34

Abstract: A processor monitors, directly or indirectly, the amount of time it takes for the memory controller to respond to one or more memory access requests. When this memory access latency indicates that a memory latency tolerance of a program thread has been exceeded, the processor can apportion additional power to the memory controller, thereby increasing the speed with which the memory controller can process memory access requests.

Abstract translation: 处理器直接或间接地监视内存控制器响应一个或多个存储器访问请求所花费的时间。 当该存储器访问延迟指示已经超过程序线程的存储器延迟容差时，处理器可以向存储器控制器分配额外的电力，从而提高存储器控制器可以处理存储器访问请求的速度。

公开(公告)号：US09372803B2

公开(公告)日：2016-06-21

申请号：US13722808

申请日：2012-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Srilatha Manne ,  Michael Schulte ,  Lloyd Bircher ,  Madhu Saravana Sibi Govindan ,  Yasuko Eckert

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0806 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.

Abstract translation: 提出了一种系统和方法。 一些实施例包括处理单元，耦合到处理单元的至少一个存储器以及耦合到处理单元并被分成一系列块的至少一个高速缓存，其中该系列高速缓存块中的至少一个包括被识别为 处于修改状态。 通过基于回写策略将数据写入至少一个存储器来刷新修改的状态数据，并且策略的侵略性基于至少一个因素，包括空闲核心数量，最后一个高速缓存刷新的接近度， 与数据相关联的线程的活动，以及哪些核心是空闲的，以及空闲核心是否与数据相关联。

公开(公告)号：US20140181413A1

公开(公告)日：2014-06-26

申请号：US13722808

申请日：2012-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Srilatha Manne ,  Michael Schulte ,  Lloyd Bircher ,  Madhu Saravana Sibi Govindan ,  Yasuko Eckert

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0806 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.

Abstract translation: 提出了一种系统和方法。 一些实施例包括处理单元，耦合到处理单元的至少一个存储器以及耦合到处理单元并被分成一系列块的至少一个高速缓存，其中该系列高速缓存块中的至少一个包括被识别为 处于修改状态。 通过基于回写策略将数据写入至少一个存储器来刷新修改的状态数据，并且策略的侵略性基于至少一个因素，包括空闲核心数量，最后一个高速缓存刷新的接近度， 与数据相关联的线程的活动，以及哪些核心是空闲的，以及空闲核心是否与数据相关联。