公开(公告)号：US20240220251A1

公开(公告)日：2024-07-04

申请号：US18147075

申请日：2022-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew R. Poremba ,  Ersin Cukurtas

IPC: G06F9/30 ,  G06F7/02

CPC classification number: G06F9/3004 ,  G06F7/02 ,  G06F9/3009

Abstract: In accordance with described techniques for processing-in-memory (PIM) search stop control, a computing system or computing device includes a memory system that includes a stop condition check component, which receives an instruction that includes a programmed check value. The stop condition check component compares the programmed check value to outputs of a PIM component, and the stop condition check component initiates a stop instruction to stop the PIM component from processing subsequent computations based on an output of the PIM component matching the programmed check value.

公开(公告)号：US10719441B1

公开(公告)日：2020-07-21

申请号：US16274146

申请日：2019-02-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Jieming Yin ,  Yasuko Eckert ,  Matthew R. Poremba ,  Steven E. Raasch ,  Doug Hunt

IPC: G06F12/0802

Abstract: An electronic device handles memory access requests for data in a memory. The electronic device includes a memory controller for the memory, a last-level cache memory, a request generator, and a predictor. The predictor determines a likelihood that a cache memory access request for data at a given address will hit in the last-level cache memory. Based on the likelihood, the predictor determines: whether a memory access request is to be sent by the request generator to the memory controller for the data in parallel with the cache memory access request being resolved in the last-level cache memory, and, when the memory access request is to be sent, a type of memory access request that is to be sent. When the memory access request is to be sent, the predictor causes the request generator to send a memory request of the type to the memory controller.

公开(公告)号：US20230205705A1

公开(公告)日：2023-06-29

申请号：US17561406

申请日：2021-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew R. Poremba ,  Alexandru Dutu ,  Sooraj Puthoor

IPC: G06F12/10

CPC classification number: G06F12/10

Abstract: An approach provides indirect addressing support for PIM. Indirect PIM commands include address translation information that allows memory modules to perform indirect addressing. Processing logic in a memory module processes an indirect PIM command and retrieves, from a first memory location, a virtual address of a second memory location. The processing logic calculates a corresponding physical address for the virtual address using the address translation information included with the indirect PIM command and retrieves, from the second memory location, a virtual address of a third memory location. This process is repeated any number of times until one or more indirection stop criteria are satisfied. The indirection stop criteria stop the process when work has been completed normally or to prevent errors. Implementations include the processing logic in the memory module working in cooperation with a memory controller to perform indirect addressing.

公开(公告)号：US20200257623A1

公开(公告)日：2020-08-13

申请号：US16274146

申请日：2019-02-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Jieming Yin ,  Yasuko Eckert ,  Matthew R. Poremba ,  Steven E. Raasch ,  Doug Hunt

IPC: G06F12/0802

Abstract: An electronic device handles memory access requests for data in a memory. The electronic device includes a memory controller for the memory, a last-level cache memory, a request generator, and a predictor. The predictor determines a likelihood that a cache memory access request for data at a given address will hit in the last-level cache memory. Based on the likelihood, the predictor determines: whether a memory access request is to be sent by the request generator to the memory controller for the data in parallel with the cache memory access request being resolved in the last-level cache memory, and, when the memory access request is to be sent, a type of memory access request that is to be sent. When the memory access request is to be sent, the predictor causes the request generator to send a memory request of the type to the memory controller.

公开(公告)号：US20240319964A1

公开(公告)日：2024-09-26

申请号：US18126107

申请日：2023-03-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Onur Kayiran ,  Lee Evan Eisen ,  Michael Estlick ,  Jay Fleischman ,  Matthew R. Poremba ,  Gabriel H. Loh

IPC: G06F7/503

CPC classification number: G06F7/503

Abstract: A processor includes one or more processor cores configured to perform accumulate top (ACCT) and accumulate bottom (ACCB) instructions. To perform such instructions, at least one processor core of the processor includes an ACCT data path that adds a first portion of a block of data to a first lane of a set of lanes of a top accumulator and adds a carry-out bit to a second lane of the set of lanes of the top accumulator. Further, the at least one processor core includes an ACCB data path that adds a second portion of the block of data to a first lane of a set of lanes of a bottom accumulator and adds a carry-out bit to a second lane of the set of lanes of the bottom accumulator.

公开(公告)号：US09367466B2

公开(公告)日：2016-06-14

申请号：US13765813

申请日：2013-02-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew R. Poremba ,  Gabriel H. Loh

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/6026

Abstract: A type of conditional probability fetcher prefetches data, such as for a cache, from another memory by maintaining information relating to memory elements in a group of memory elements fetched from the second memory. The information may be an aggregate number of memory elements that have been fetched for different memory segments in the group. The information is maintained responsive to fetching one or more memory elements from a segment of memory elements in the group of memory elements. Prefetching one or more remaining memory elements in a particular segment of memory elements from the second memory into the first memory occurs when the information relating to the memory elements in the group of memory elements indicates that a prefetching condition has been satisfied.

Abstract translation: 一种类型的条件概率提取器通过维护与从第二存储器提取的一组存储器元件中的存储器元件有关的信息，从另一存储器预取诸如用于高速缓存的数据。 信息可以是已经为组中的不同存储器段获取的存储器元素的总数。 该信息是响应于从一组存储器元件中的存储器元件的段中提取一个或多个存储器元件来保持的。 当与存储元件组中的存储元件相关的信息指示已经满足预取条件时，将存储器元件的特定段中的一个或多个剩余存储元件从第二存储器预取到第一存储器中。

公开(公告)号：US09087561B2

公开(公告)日：2015-07-21

申请号：US13724669

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthew R. Poremba ,  Gabriel H. Loh

IPC: G06F12/04 ,  G11C7/10 ,  G06F12/08

CPC classification number: G11C7/1072 ,  G06F12/0886 ,  G06F2212/1041 ,  G06F2212/601

Abstract: Data caching methods and systems are provided. A method is provided for a hybrid cache system that dynamically changes modes of one or more cache rows of a cache between an un-split mode having a first tag field and a first data field to a split mode having a second tag field, a second data field being smaller than the first data field and a mapped page field to improve the cache access efficiency of a workflow being executed in a processor. A hybrid cache system is provided in which the cache is configured to operate one or more cache rows in an un-split mode or in a split mode. The system is configured to dynamically change modes of the cache rows from the un-split mode to the split mode to improve the cache access efficiency of a workflow being executed by the processor.

Abstract translation: 提供数据缓存方法和系统。 提供了一种用于混合高速缓存系统的方法，其将具有第一标签字段和第一数据字段的未分割模式之间的高速缓存行的一个或多个高速缓存行的模式动态地改变为具有第二标签字段的分割模式，第二标记字段 数据字段小于第一数据字段和映射页面字段，以提高在处理器中正在执行的工作流的高速缓存访​​问效率。 提供了混合高速缓存系统，其中高速缓存被配置为以未分割模式或分离模式操作一个或多个高速缓存行。 该系统被配置为将缓存行的模式从未分割模式动态地改变到分割模式，以提高由处理器执行的工作流的高速缓存访​​问效率。

公开(公告)号：US09053039B2

公开(公告)日：2015-06-09

申请号：US13724867

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthew R. Poremba ,  Gabriel H. Loh

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0862 ,  Y02D10/13

Abstract: Data caching methods and systems are provided. The data cache method loads data into an installation cache and a cache (simultaneously or serially) and returns data from the installation cache when the data has not completely loaded into the cache. The data cache system includes a processor, a memory coupled to the processor, a cache coupled to the processor and the memory and an installation cache coupled to the processor and the memory. The system is configured to load data from the memory into the installation cache and the cache (simultaneously or serially) and return data from the installation cache to the processor when the data has not completely loaded into the cache.

Abstract translation: 提供数据缓存方法和系统。 数据高速缓存方法将数据加载到安装高速缓存和高速缓存（同时或连续）中，并在数据尚未完全加载到高速缓存中时从安装高速缓存返回数据。 数据缓存系统包括处理器，耦合到处理器的存储器，耦合到处理器和存储器的高速缓存以及耦合到处理器和存储器的安装高速缓存。 该系统被配置为当数据尚未完全加载到高速缓存中时，将数据从存储器加载到安装高速缓存和高速缓存（同时或串行）中，并将数据从安装高速缓存返回到处理器。

公开(公告)号：US20140181387A1

公开(公告)日：2014-06-26

申请号：US13724669

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthew R. Poremba ,  Gabriel H. Loh

IPC: G11C7/10 ,  G06F12/12

CPC classification number: G11C7/1072 ,  G06F12/0886 ,  G06F2212/1041 ,  G06F2212/601

Abstract: Data caching methods and systems are provided. A method is provided for a hybrid cache system that dynamically changes modes of one or more cache rows of a cache between an un-split mode having a first tag field and a first data field to a split mode having a second tag field, a second data field being smaller than the first data field and a mapped page field to improve the cache access efficiency of a workflow being executed in a processor. A hybrid cache system is provided in which the cache is configured to operate one or more cache rows in an un-split mode or in a split mode. The system is configured to dynamically change modes of the cache rows from the un-split mode to the split mode to improve the cache access efficiency of a workflow being executed by the processor.

Abstract translation: 提供数据缓存方法和系统。 提供了一种用于混合高速缓存系统的方法，其将具有第一标签字段和第一数据字段的未分割模式之间的高速缓存行的一个或多个高速缓存行的模式动态地改变为具有第二标签字段的分割模式，第二标记字段 数据字段小于第一数据字段和映射页面字段，以提高在处理器中正在执行的工作流的高速缓存访​​问效率。 提供了混合高速缓存系统，其中高速缓存被配置为以未分割模式或分离模式操作一个或多个高速缓存行。 该系统被配置为将缓存行的模式从未分割模式动态地改变到分割模式，以提高由处理器执行的工作流的高速缓存访​​问效率。

公开(公告)号：US11513801B2

公开(公告)日：2022-11-29

申请号：US16127093

申请日：2018-09-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Adithya Yalavarti ,  John Kalamatianos ,  Matthew R. Poremba

IPC: G06F9/38 ,  G06F1/3287 ,  G06F9/30

Abstract: An electronic device is described that handles control transfer instructions (CTIs) when executing instructions in program code. The electronic device has a processor that includes a branch prediction functional block and a sequential fetch logic functional block. The sequential fetch logic functional block determines, based on a record associated with a CTI, that a specified number of fetch groups of instructions that were previously determined to include no CTIs are to be fetched for execution in sequence following the CTI. When each of the specified number of fetch groups is fetched and prepared for execution, the sequential fetch logic prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that fetch group.