Patent search ap:("Advanced Micro Devices Page Inc.") AND inv:"Doug Hunt"

1.

发明授权
Using predictions of outcomes of cache memory access requests for controlling whether a request generator sends memory access requests to a memory in parallel with cache memory access requests 有权

公开(公告)号：US10719441B1

公开(公告)日：2020-07-21

申请号：US16274146

申请日：2019-02-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Jieming Yin , Yasuko Eckert , Matthew R. Poremba , Steven E. Raasch , Doug Hunt

IPC: G06F12/0802

Abstract: An electronic device handles memory access requests for data in a memory. The electronic device includes a memory controller for the memory, a last-level cache memory, a request generator, and a predictor. The predictor determines a likelihood that a cache memory access request for data at a given address will hit in the last-level cache memory. Based on the likelihood, the predictor determines: whether a memory access request is to be sent by the request generator to the memory controller for the data in parallel with the cache memory access request being resolved in the last-level cache memory, and, when the memory access request is to be sent, a type of memory access request that is to be sent. When the memory access request is to be sent, the predictor causes the request generator to send a memory request of the type to the memory controller.

2.

发明申请
Using Predictions of Outcomes of Cache Memory Access Requests for Contolling Whether A Request Generator Sends Memory Access Requests To A Memory In Parallel With Cache Memory Access Requests 审中-公开

公开(公告)号：US20200257623A1

公开(公告)日：2020-08-13

申请号：US16274146

申请日：2019-02-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Jieming Yin , Yasuko Eckert , Matthew R. Poremba , Steven E. Raasch , Doug Hunt

IPC: G06F12/0802

Abstract: An electronic device handles memory access requests for data in a memory. The electronic device includes a memory controller for the memory, a last-level cache memory, a request generator, and a predictor. The predictor determines a likelihood that a cache memory access request for data at a given address will hit in the last-level cache memory. Based on the likelihood, the predictor determines: whether a memory access request is to be sent by the request generator to the memory controller for the data in parallel with the cache memory access request being resolved in the last-level cache memory, and, when the memory access request is to be sent, a type of memory access request that is to be sent. When the memory access request is to be sent, the predictor causes the request generator to send a memory request of the type to the memory controller.

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