公开(公告)号：US10157787B2

公开(公告)日：2018-12-18

申请号：US15384219

申请日：2016-12-19

Applicant: APPLIED MATERIALS, INC.

Inventor： Jin Hee Park ,  Tae Hong Ha ,  Sang-Hyeob Lee ,  Thomas Jongwan Kwon ,  Jaesoo Ahn ,  Xianmin Tang ,  Er-Xuan Ping ,  Sree Kesapragada

IPC: H01L21/768 ,  H01L21/285 ,  C23C16/48 ,  C23C16/455 ,  C23C16/04 ,  C23C16/16 ,  C23C16/18 ,  C23C16/56 ,  H01L21/67 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582

Abstract: Methods and apparatus for depositing a cobalt layer in a feature, such as, a word line formed in a substrate, are provided herein. In some embodiments, method of processing a substrate includes: exposing a substrate at a first temperature to a cobalt containing precursor to deposit a cobalt layer within a word line feature formed in the substrate, wherein the word line feature is part of a 3D NAND device; and annealing the substrate to remove contaminants from the cobalt layer and to reflow the cobalt layer into the word line feature, wherein the substrate is at a second temperature greater than the first temperature during the annealing.

公开(公告)号：US20180342396A1

公开(公告)日：2018-11-29

申请号：US15605769

申请日：2017-05-25

Applicant: Applied Materials, Inc.

Inventor： Keith Tatseun Wong ,  Thomas Jongwan Kwon ,  Sean Kang ,  Ellie Y. Yieh

IPC: H01L21/285 ,  H01L27/115 ,  H01L21/768 ,  C23C16/08 ,  C23C16/56

Abstract: Methods and systems relating to processes for treating a tungsten film on a workpiece including supporting the workpiece in a chamber, introducing hydrogen gas into the chamber and establishing a pressure of at least 5 atmospheres, and exposing the tungsten film on the workpiece to the hydrogen gas while the pressure in the chamber is at least 5 atmospheres.

公开(公告)号：US11705337B2

公开(公告)日：2023-07-18

申请号：US16696229

申请日：2019-11-26

Applicant: Applied Materials, Inc.

Inventor： Keith Tatseun Wong ,  Thomas Jongwan Kwon ,  Sean Kang ,  Ellie Y. Yieh

IPC: H01L21/285 ,  C23C16/14 ,  H10B69/00 ,  C23C16/08 ,  C23C16/56 ,  H01L21/768 ,  H10B41/20 ,  H10B43/20

CPC classification number: H01L21/28556 ,  C23C16/08 ,  C23C16/14 ,  C23C16/56 ,  H01L21/28568 ,  H01L21/76883 ,  H10B69/00 ,  H10B41/20 ,  H10B43/20

Abstract: An annealing system is provided that includes a chamber body that defines a chamber, a support to hold a workpiece and a robot to insert the workpiece into the chamber. The annealing system also includes a first gas supply to provide a hydrogen gas, a pressure source coupled to the chamber to raise a pressure in the chamber to at least 5 atmospheres, and a controller configured to cause the robot to transport a workpiece having a metal film thereon into the chamber, where the metal film contains fluorine on a surface or embedded within the metal film, to cause the first gas supply to supply the hydrogen gas to the chamber and form atomic hydrogen therein, and to cause the pressure source to raise a pressure in the chamber to at least 5 atmospheres while the workpiece is held on the support in the chamber.

公开(公告)号：US10446392B2

公开(公告)日：2019-10-15

申请号：US15881405

申请日：2018-01-26

Applicant: Applied Materials, Inc.

Inventor： Sungwon Jun ,  Saurabh Chopra ,  Thomas Jongwan Kwon ,  Er-Xuan Ping

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/28 ,  C23C16/06 ,  H01L29/423 ,  C23C16/04 ,  C23C16/24 ,  C23C16/34 ,  C23C16/40 ,  C23C16/452 ,  C23C16/50 ,  C30B25/18 ,  C30B29/52 ,  C30B29/60 ,  H01L27/11556

Abstract: A method of forming a 3D NAND structure having self-aligned nanodots includes depositing alternating layers of an oxide and a nitride on a substrate; at least partially recessing the nitride layers; and forming SiGe nanodots on the nitride layers. A method of forming a 3D NAND structure having self-aligned nanodots includes depositing alternating layers of an oxide and a nitride on a substrate; at least partially recessing the nitride layers; and forming SiGe nanodots on the nitride layers by a process including maintaining a temperature of the substrate below about 560° C.; flowing a silicon epitaxy precursor into the chamber; forming a silicon epitaxial layer on the substrate at the nitride layers; flowing germanium gas into the chamber with the silicon epitaxy precursor; and forming a silicon germanium epitaxial layer on the substrate at the nitride layers.

公开(公告)号：US10714388B2

公开(公告)日：2020-07-14

申请号：US16222630

申请日：2018-12-17

Applicant: APPLIED MATERIALS, INC.

Inventor： Jin Hee Park ,  Tae Hong Ha ,  Sang-Hyeob Lee ,  Thomas Jongwan Kwon ,  Jaesoo Ahn ,  Xianmin Tang ,  Er-Xuan Ping ,  Sree Kesapragada

IPC: H01L21/768 ,  H01L21/285 ,  C23C16/48 ,  C23C16/455 ,  C23C16/04 ,  C23C16/16 ,  C23C16/18 ,  C23C16/56 ,  H01L21/67 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582

Abstract: Methods and apparatus for depositing a cobalt layer in a feature, such as, a word line formed in a substrate, are provided herein. In some embodiments, method of processing a substrate includes: exposing a substrate at a first temperature to a cobalt containing precursor to deposit a cobalt layer within a word line feature formed in the substrate, wherein the word line feature is part of a 3D NAND device; and annealing the substrate to remove contaminants from the cobalt layer and to reflow the cobalt layer into the word line feature, wherein the substrate is at a second temperature greater than the first temperature during the annealing.

公开(公告)号：US10410864B2

公开(公告)日：2019-09-10

申请号：US15988830

申请日：2018-05-24

Applicant: Applied Materials, Inc.

Inventor： Thomas Jongwan Kwon ,  Rui Cheng ,  Abhijit Basu Mallick ,  Er-Xuan Ping ,  Jaesoo Ahn

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L27/11582 ,  H01L49/02

Abstract: Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.

公开(公告)号：US10246772B2

公开(公告)日：2019-04-02

申请号：US15063569

申请日：2016-03-08

Applicant: Applied Materials, Inc.

Inventor： Praket P. Jha ,  Allen Ko ,  Xinhai Han ,  Thomas Jongwan Kwon ,  Bok Hoen Kim ,  Byung Ho Kil ,  Ryeun Kim ,  Sang Hyuk Kim

IPC: C23C16/34 ,  C23C16/40 ,  H05H1/24 ,  H01L21/02 ,  C23C16/455 ,  H01L21/311 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method for forming a high aspect ratio feature is disclosed. The method includes depositing one or more silicon oxide/silicon nitride containing stacks on a substrate by depositing a first film layer on the substrate from a first plasma and depositing a second film layer having a refractive index on the first film layer from a second plasma. A predetermined number of first film layers and second film layers are deposited on the substrate. The first film layer and the second film layer are either a silicon oxide layer or a silicon nitride layer and the first film layer is different from the second film layer. The method further includes depositing a third film layer from a third plasma and depositing a fourth film layer on the third film layer from a fourth plasma. The fourth film layer has a refractive index greater than the first refractive index.

公开(公告)号：US11365476B2

公开(公告)日：2022-06-21

申请号：US16269337

申请日：2019-02-06

Applicant: Applied Materials, Inc.

Inventor： Praket P. Jha ,  Allen Ko ,  Xinhai Han ,  Thomas Jongwan Kwon ,  Bok Hoen Kim ,  Byung Ho Kil ,  Ryeun Kim ,  Sang Hyuk Kim

IPC: H01L27/11556 ,  C23C16/34 ,  H01L21/02 ,  C23C16/40 ,  C23C16/455 ,  H01L21/311 ,  H01L27/11582

Abstract: The present disclosure generally relate to thin films incorporating high aspect ratio feature definitions and methods for forming the same. As gate height increases, 3D NAND gate stacks are subject to higher aspect ratio etching. Due to the current limitations of etching techniques, the vertical etch profile typically tapers as the depth into the gate stack increases. The inventors have devised a unique deposition scheme that compensates for etch performance degradation in deep trenches by a novel plasma-enhanced chemical vapor deposition (PECVD) film deposition method. The inventors have found that by grading various properties (e.g., refractive index, stress of the film, dopant concentration in the film) of the as-deposited films (e.g., silicon nitride) a more uniform etch profile can be achieved by compensating for variations in both dry and wet etch rates.

公开(公告)号：US10825681B2

公开(公告)日：2020-11-03

申请号：US15493690

申请日：2017-04-21

Applicant: Applied Materials, Inc.

Inventor： Thomas Jongwan Kwon ,  Sungwon Jun

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/16

Abstract: Provided are an improved memory device and a method of manufacturing the same. In one embodiment, the memory device may include a vertical stack of alternating oxide layer and nitride layer, the vertical stack having a channel region formed therethrough, a plurality of nanostructures selectively formed on nitride layer of the vertical stack, and a gate oxide layer disposed on exposed surfaces of the channel region, the gate oxide layer encapsulating the plurality of nanostructures formed on the nitride layer. The nanostructures may be a group IV semiconductor compound such as silicon germanium (SiGe).

公开(公告)号：US09991118B2

公开(公告)日：2018-06-05

申请号：US15398591

申请日：2017-01-04

Applicant: Applied Materials, Inc.

Inventor： Thomas Jongwan Kwon ,  Rui Cheng ,  Abhijit Basu Mallick ,  Er-Xuan Ping ,  Jaesoo Ahn

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L27/11582 ,  H01L49/02

CPC classification number: H01L21/0338 ,  H01L21/02109 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/11582 ,  H01L28/00

Abstract: Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.