公开(公告)号：US20240371654A1

公开(公告)日：2024-11-07

申请号：US18142940

申请日：2023-05-03

Applicant: Applied Materials, Inc.

Inventor： Qihao ZHU ,  Chi Hong CHING ,  Liqi WU ,  Tsungjui LIU ,  Gaurav THAREJA ,  Xinke WANG ,  Feng Q. LIU ,  Xi CEN ,  Kai WU ,  Yixiong YANG ,  Yuanhung LIU ,  Jiang LU ,  Rongjun WANG ,  Xianmin TANG

IPC: H01L21/3213 ,  H01L21/02 ,  H01L21/768

Abstract: A method of filling a feature in a semiconductor structure with metal includes depositing a metal cap layer on a bottom surface of a feature formed within a dielectric layer and top surfaces of the dielectric layer, partially filling the feature from the bottom surface with a flowable polymer layer, performing a metal pullback process to remove the metal cap layer on the top surfaces of the dielectric layer selectively to the dielectric layer, wherein the metal pullback process includes a first etch process including a chemical etch process using molybdenum hexafluoride (MoF6) to remove the metal cap layer selectively to the dielectric layer, and a second etch process to remove residues on etched surfaces of the dielectric layer, removing the flowable polymer layer, pre-cleaning a surface of the metal cap layer, and filling the feature from the surface of the metal cap layer with metal fill material.

公开(公告)号：US20250157856A1

公开(公告)日：2025-05-15

申请号：US18912536

申请日：2024-10-10

Applicant: Applied Materials, Inc.

Inventor： Jiajie CEN ,  Zheng JU ,  Feng Q. LIU ,  Ying-Bing JIANG ,  Shiyu YUE ,  Xianmin TANG

IPC: H01L21/768 ,  C23C16/14 ,  C23C16/50

Abstract: Embodiments of the invention provide a method of forming a molybdenum (Mo) capping layer that is used to prevent copper diffusion in interconnect boundary regions of a formed semiconductor device. The molybdenum capping will improve copper boundary region properties to promote adhesion, decrease diffusion and copper agglomeration. Embodiments provide that a molybdenum capping layer may be selectively deposited on a surface of a copper interconnect structures formed in a dielectric layer formed on a substrate.

公开(公告)号：US20240186181A1

公开(公告)日：2024-06-06

申请号：US18074335

申请日：2022-12-02

Applicant: Applied Materials, Inc.

Inventor： Ge QU ,  Qihao ZHU ,  Zheng JU ,  Yang ZHOU ,  Jiajie CEN ,  Feng Q. LIU ,  Zhiyuan WU ,  Feng CHEN ,  Kevin KASHEFI ,  Xianmin TANG ,  Jeffrey W. ANTHIS ,  Mark Joseph SALY

IPC: H01L21/768 ,  H01L21/3205

CPC classification number: H01L21/76849 ,  H01L21/32051 ,  H01L21/76877

Abstract: Methods to deposit a metal cap for an interconnect are disclosed. In embodiments, a method comprises contacting the substrate with an alkyl halide and a ruthenium metal precursor to form a metal cap for an interconnect.

公开(公告)号：US20240290655A1

公开(公告)日：2024-08-29

申请号：US18115561

申请日：2023-02-28

Applicant: Applied Materials, Inc.

Inventor： Zheng JU ,  Zhiyuan WU ,  Jiajie CEN ,  Feng Q. LIU ,  Feng CHEN

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76844 ,  H01L21/76846 ,  H01L21/76879 ,  H01L23/5226 ,  H01L21/76862 ,  H01L23/53238 ,  H01L23/53266

Abstract: A method of selectively filling a via with a simultaneous liner deposition in a semiconductor structure includes forming a passivation layer selectively on an exposed surface of a conductive layer within a via formed in a dielectric layer formed over the conductive layer, forming a barrier layer selectively on inner sidewalls of the via and a trench formed in the dielectric layer, selectively filling the via with a first conductive material at least partially and simultaneously depositing the first conductive material on the barrier layer on the inner sidewalls of the via and the trench, to form a liner on the inner sidewalls of the via and the trench, and filling the remaining of the via and the trench with a second conductive material.

公开(公告)号：US20220193859A1

公开(公告)日：2022-06-23

申请号：US17127065

申请日：2020-12-18

Applicant: Applied Materials, Inc.

Inventor： Xingfeng WANG ,  Jianshe TANG ,  Feng Q. LIU ,  David M. GAGE ,  Stephen JEW

IPC: B24B37/04 ,  B24B37/10 ,  B24B37/20 ,  B24B57/02

Abstract: A polishing station for polishing a substrate using a polishing slurry is disclosed. The polishing station includes a substrate carrier having a substrate-receiving surface and a rotatable platen having a polishing pad disposed on a platen surface, where the polishing pad has a polishing surface facing the substrate-receiving surface. The polishing station includes an electromagnetic assembly disposed over the platen surface. The electromagnetic assembly includes an array of electromagnetic devices that are each operable to generate a magnetic field that is configured to pass through the polishing surface. The magnetic fields generated by the array of electromagnetic devices are oriented and configured to induce an electromagnetic force on a plurality of charged particles disposed in a polishing slurry disposed on the polishing surface. The applied magnetic field is configured to induce movement of the plurality of charged particles in a direction parallel or orthogonal to the polishing surface.

公开(公告)号：US20170098540A1

公开(公告)日：2017-04-06

申请号：US15280161

申请日：2016-09-29

Applicant: APPLIED MATERIALS, INC.

Inventor： Xiangjin XIE ,  Feng Q. LIU ,  Daping YAO ,  Alexander JANSEN ,  Joung Joo LEE ,  Adolph Miller ALLEN ,  Xianmin TANG ,  Mei CHANG

IPC: H01L21/02 ,  B08B5/00 ,  B08B9/027 ,  B08B7/00

CPC classification number: H01L21/02068 ,  B08B3/00 ,  B08B3/106 ,  B08B5/00 ,  B08B7/0035 ,  B08B9/00 ,  B08B9/027 ,  C23G1/24 ,  F01D5/005 ,  F05D2230/90 ,  H01L21/02063 ,  H01L21/76814

Abstract: Methods for processing a substrate are provided herein. In some embodiments, a method of processing a substrate includes: heating a substrate disposed within a processing volume of a substrate processing chamber to a temperature of up to about 400 degrees Celsius, wherein the substrate comprises a first surface, an opposing second surface, and an opening formed in the first surface and extending towards the opposing second surface, and wherein the second surface comprises a conductive material disposed in the second surface and aligned with the opening; and exposing the substrate to a process gas comprising about 80 to about 100 wt. % of an alcohol to reduce a contaminated surface of the conductive material.