公开(公告)号：US12073806B2

公开(公告)日：2024-08-27

申请号：US17134770

申请日：2020-12-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Ashish Jain ,  Dhirendra Partap Singh Rana ,  Samuel Naffziger ,  Gia Tung Phan ,  Benjamin Tsien

IPC: G09G3/36 ,  G06F1/3234 ,  G06F12/0811 ,  G06F12/0895 ,  G09G3/20

CPC classification number: G09G3/3618 ,  G06F1/3265 ,  G06F12/0811 ,  G06F12/0895 ,  G09G3/2092 ,  G09G2330/021

Abstract: Refreshing displays using on-die cache, including: determining that a static display condition has been met; storing, in cache memory of a processor, first display data; and displaying the first display data from the cache memory.

公开(公告)号：US10452554B2

公开(公告)日：2019-10-22

申请号：US15094391

申请日：2016-04-08

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ihab Amer ,  Khaled Mammou ,  Haibo Liu ,  Edward Harold ,  Fabio Gulino ,  Samuel Naffziger ,  Gabor Sines ,  Lawrence A. Bair ,  Andy Sung ,  Lei Zhang

IPC: G06F12/08 ,  G11C11/417 ,  G06F12/0877 ,  G06F12/0893 ,  G11C5/14

Abstract: Systems, apparatuses and methods of adaptively controlling a cache operating voltage are provided that comprise receiving indications of a plurality of cache usage amounts. Each cache usage amount corresponds to an amount of data to be accessed in a cache by one of a plurality of portions of a data processing application. The plurality of cache usage amounts are determining based on the received indications of the plurality of cache usage amounts. A voltage level applied to the cache is adaptively controlled based on one or more of the plurality of determined cache usage amounts. Memory access to the cache is controlled to be directed to a non-failing portion of the cache at the applied voltage level.

公开(公告)号：US20180364782A1

公开(公告)日：2018-12-20

申请号：US16011476

申请日：2018-06-18

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Leonardo De Paula Rosa Piga ,  Samuel Naffziger ,  Ivan Matosevic ,  Indrani Paul

IPC: G06F1/32

Abstract: A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.

公开(公告)号：US20170293564A1

公开(公告)日：2017-10-12

申请号：US15094391

申请日：2016-04-08

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ihab Amer ,  Khaled Mammou ,  Haibo Liu ,  Edward Harold ,  Fabio Gulino ,  Samuel Naffziger ,  Gabor Sines ,  Lawrence A. Bair ,  Andy Sung ,  Lei Zhang

IPC: G06F12/08 ,  G11C11/417

CPC classification number: G06F12/0877 ,  G06F12/0893 ,  G06F2212/1028 ,  G06F2212/221 ,  G06F2212/60 ,  G11C5/148 ,  G11C11/417

Abstract: Systems, apparatuses and methods of adaptively controlling a cache operating voltage are provided that comprise receiving indications of a plurality of cache usage amounts. Each cache usage amount corresponds to an amount of data to be accessed in a cache by one of a plurality of portions of a data processing application. The plurality of cache usage amounts are determining based on the received indications of the plurality of cache usage amounts. A voltage level applied to the cache is adaptively controlled based on one or more of the plurality of determined cache usage amounts. Memory access to the cache is controlled to be directed to a non-failing portion of the cache at the applied voltage level.

公开(公告)号：US20240324248A1

公开(公告)日：2024-09-26

申请号：US18474179

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： John Wuu ,  Kevin Gillespie ,  Samuel Naffziger ,  Spence Oliver ,  Rajit Seahra ,  Regina T. Schmidt ,  Raja Swaminathan ,  Omar Zia

IPC: H10B80/00 ,  H01L23/544 ,  H01L25/00 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L23/544 ,  H01L25/18 ,  H01L25/50 ,  H01L23/481 ,  H01L23/5286 ,  H01L24/06 ,  H01L24/08 ,  H01L2223/54433 ,  H01L2224/06181 ,  H01L2224/08145

Abstract: A method for die pair partitioning can include providing a circuit die. The method can additionally include providing one or more additional circuit die having one or more fuses positioned therein, wherein the one or more fuses identify the circuit die. The method can also include connecting the one or more additional circuit die to the circuit die. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11054883B2

公开(公告)日：2021-07-06

申请号：US16011476

申请日：2018-06-18

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Leonardo De Paula Rosa Piga ,  Samuel Naffziger ,  Ivan Matosevic ,  Indrani Paul

IPC: G06F1/324

Abstract: A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.

公开(公告)号：US11960340B2

公开(公告)日：2024-04-16

申请号：US17521578

申请日：2021-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric J. Chapman ,  Stephen Victor Kosonocky ,  Kaushik Mazumdar ,  Vydhyanathan Kalyanasundharam ,  Samuel Naffziger ,  Eric M. Scott

IPC: G06F1/30

CPC classification number: G06F1/30

Abstract: A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.

公开(公告)号：US11462294B2

公开(公告)日：2022-10-04

申请号：US17121110

申请日：2020-12-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Ashish Jain ,  Sriram Sundaram ,  Samuel Naffziger

IPC: G11C7/10 ,  G11C29/50 ,  G11C7/22 ,  H03K3/03

Abstract: The low end operating voltage of an integrated circuit is adjusted. Oscillations are counted at a ring oscillator on the integrated circuit over a designated period of clock cycles. Based on the number of oscillations, a prediction model associated with a first set of device degradation data and a second set of static random-access memory (SRAM) low end operating voltage data is used to select a low end operating voltage limit for a processor on the integrated circuit. The low end operating voltage of the processor is set based on the selected low end operating voltage limit. These steps are repeated multiple times during operation of the processor. A method of testing integrated circuits to provide the data employed to produce the prediction model is also provided.

公开(公告)号：US10303398B2

公开(公告)日：2019-05-28

申请号：US15794457

申请日：2017-10-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Wuu ,  Michael K. Ciraula ,  Russell Schreiber ,  Samuel Naffziger

IPC: G11C5/06 ,  G06F3/06 ,  G06F12/1009

Abstract: A processing system includes a compute die and a stacked memory stacked with the compute die. The stacked memory includes a first memory die and a second memory die stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.

公开(公告)号：US20150241955A1

公开(公告)日：2015-08-27

申请号：US14190803

申请日：2014-02-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Stephen Kosonocky ,  Samuel Naffziger

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3296 ,  G06F1/206 ,  G06F1/3206 ,  Y02D10/16 ,  Y02D10/172

Abstract: Some embodiments of a processing device include one or more power supply monitors to provide one or more counts representative of one or more operating frequencies of one or more circuit blocks based on a voltage supplied to the circuit block(s). Some embodiments of the processing device also include a system management unit to determine an initial voltage supplied to the circuit block(s) based on a target count and to reduce the voltage supplied to the circuit block(s) from the initial voltage in response to the count(s) generated by the power supply monitor(s) exceeding the target count.

Abstract translation: 处理装置的一些实施例包括一个或多个电源监视器，以基于提供给电路块的电压来提供表示一个或多个电路块的一个或多个工作频率的一个或多个计数。 处理装置的一些实施例还包括系统管理单元，用于基于目标计数确定提供给电路块的初始电压，并且响应于初始电压减小提供给电路块的电压与初始电压 电源监视器产生的计数超过目标计数。