公开(公告)号：US10303398B2

公开(公告)日：2019-05-28

申请号：US15794457

申请日：2017-10-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Wuu ,  Michael K. Ciraula ,  Russell Schreiber ,  Samuel Naffziger

IPC: G11C5/06 ,  G06F3/06 ,  G06F12/1009

Abstract: A processing system includes a compute die and a stacked memory stacked with the compute die. The stacked memory includes a first memory die and a second memory die stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.

公开(公告)号：US09916246B1

公开(公告)日：2018-03-13

申请号：US15238209

申请日：2016-08-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Carson Donahue Henrion ,  Michael K. Ciraula ,  Gregg Donley ,  Alok Garg ,  Eric Busta

IPC: G06F12/00 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/128

CPC classification number: G06F12/0811 ,  G06F12/0828 ,  G06F12/0833 ,  G06F2212/621 ,  G06F2212/69 ,  G06F2212/70

Abstract: A processing system includes a shadow tag memory, which stores a plurality of entries containing coherency information for the cachelines residing at the various levels of private caches. If a cache miss occurs at a private cache, or if coherency information for a cacheline requires updating, a probe is sent to the shadow tag memory maintained at the shared cache to determine whether the requested (or affected) cacheline is stored at another private cache. The probe includes a tag which can be divided into two or more portions. To more efficiently compare the probe tag to the shadow tag entries, the comparison is performed in multiple stages based on the portions of the probe tag.

公开(公告)号：US11361819B2

公开(公告)日：2022-06-14

申请号：US15841649

申请日：2017-12-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Andrew Robison ,  Michael K. Ciraula ,  Eric Busta ,  Carson Donahue Henrion

IPC: G11C11/419 ,  G11C11/418 ,  G11C7/12

Abstract: A processing system reduces by staging precharging of bitlines of a memory. In a static random access memory (SRAM) array, the voltage level on every bitline in the array is precharged to a reference voltage (VDD) rail voltage before a memory access. To facilitate reduction of current spikes from precharging, a precharge control unit groups entries of a RAM into a plurality of subsets, or regions, and applies a different precharge signal for precharging bitlines associated with each subset. Application of the precharge signals to the respective subsets over time results in smaller current spikes than simultaneous application of precharge signals to all of the bitlines.

公开(公告)号：US10452505B2

公开(公告)日：2019-10-22

申请号：US15849071

申请日：2017-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael K. Ciraula

IPC: G06F11/22 ,  H03M13/01 ,  G06F11/10 ,  G06F11/34 ,  G11C29/12 ,  G06F11/07 ,  G11C29/10 ,  G06F9/30

Abstract: A memory system includes a non-volatile memory unit, a content-addressable memory unit coupled to the non-volatile memory unit, and an error injection logic unit coupled to the non-volatile memory unit and the content addressable memory unit. The non-volatile memory unit is programmed to allow a first error injection onto a first data word using the error injection logic unit. The error injection logic in combination with the content addressable memory unit replaces a bit cell in the memory system. The memory system performs an evaluation of various error detection and correction techniques.

公开(公告)号：US20180052770A1

公开(公告)日：2018-02-22

申请号：US15238209

申请日：2016-08-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Carson Donahue Henrion ,  Michael K. Ciraula ,  Gregg Donley ,  Alok Garg ,  Eric Busta

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/128

CPC classification number: G06F12/0811 ,  G06F12/0828 ,  G06F12/0833 ,  G06F2212/621 ,  G06F2212/69 ,  G06F2212/70

Abstract: A processing system includes a shadow tag memory, which stores a plurality of entries containing coherency information for the cachelines residing at the various levels of private caches. If a cache miss occurs at a private cache, or if coherency information for a cacheline requires updating, a probe is sent to the shadow tag memory maintained at the shared cache to determine whether the requested (or affected) cacheline is stored at another private cache. The probe includes a tag which can be divided into two or more portions. To more efficiently compare the probe tag to the shadow tag entries, the comparison is performed in multiple stages based on the portions of the probe tag.

公开(公告)号：US20190268086A1

公开(公告)日：2019-08-29

申请号：US15903253

申请日：2018-02-23

Applicant: Advanced Micro Devices, Inc.

Inventor： John Wuu ,  Samuel Naffziger ,  Michael K. Ciraula ,  Russell Schreiber

IPC: H04J99/00 ,  H01L23/48 ,  H01L23/00

Abstract: An integrated circuit includes first and second through-silicon via (TSV) circuits and a steering logic circuit. The first TSV circuit has a first TSV and a first multiplexer for selecting between a first TSV data signal received from the first TSV and a first local data signal for transmission to a first TSV output terminal. The second TSV circuit includes a second TSV and a second multiplexer for selecting between a second TSV data signal received from the second TSV and the first local data signal for transmission to a second TSV output terminal. The steering logic circuit controls the first multiplexer to select the first local data signal and the second multiplexer to select the second TSV data signal in a first mode, and the first multiplexer to select the first TSV data signal and the second multiplexer to select the first local data signal in a second mode.

公开(公告)号：US10509752B2

公开(公告)日：2019-12-17

申请号：US15964647

申请日：2018-04-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  John Wuu ,  Michael K. Ciraula ,  Patrick J. Shyvers

IPC: G11C5/06 ,  G06F13/38 ,  G06F13/42 ,  H01L25/065 ,  G06F13/40

Abstract: A data processing system includes a processing unit that forms a base die and has a group of through-silicon vias (TSVs), and is connected to a memory system. The memory system includes a die stack that includes a first die and a second die. The first die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads. The group of micro-bump landing pads are connected to the group of TSVs of the processing unit using a corresponding group of micro-bumps. The first die has a group of memory die TSVs. The subsequent die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads connected to the group of TSVs of the first die. The first die communicates with the processing unit using first cycle timing, and with the subsequent die using second cycle timing.

公开(公告)号：US20190332561A1

公开(公告)日：2019-10-31

申请号：US15964647

申请日：2018-04-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  John Wuu ,  Michael K. Ciraula ,  Patrick J. Shyvers

IPC: G06F13/38 ,  G06F13/42 ,  G06F13/40 ,  H01L25/065

Abstract: A data processing system includes a processing unit that forms a base die and has a group of through-silicon vias (TSVs), and is connected to a memory system. The memory system includes a die stack that includes a first die and a second die. The first die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads. The group of micro-bump landing pads are connected to the group of TSVs of the processing unit using a corresponding group of micro-bumps. The first die has a group of memory die TSVs. The subsequent die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads connected to the group of TSVs of the first die. The first die communicates with the processing unit using first cycle timing, and with the subsequent die using second cycle timing.