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    SYSTEM AND METHOD FOR MULTIPLEXER TREE INDEXING
    2.
    发明申请
    SYSTEM AND METHOD FOR MULTIPLEXER TREE INDEXING 有权

    公开(公告)号：US20220237164A1

    公开(公告)日：2022-07-28

    申请号：US17721748

    申请日：2022-04-15

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Steven R. Havlir ,  Patrick J. Shyvers

    IPC: G06F16/22

    Abstract: Described herein is a system and method for multiplexer tree (muxtree) indexing. Muxtree indexing performs hashing and row reduction in parallel by use of at least one bit in a lookup address at least once in a particular path of the muxtree. The muxtree indexing generates a different final index as compared to conventional hashed indexing but still results in a fair hash, where all table entries get used with equal distribution with uniformly random selects.

    MEMORY INCLUDING SIDE-CAR ARRAYS WITH IRREGULAR SIZED ENTRIES
    4.
    发明申请
    MEMORY INCLUDING SIDE-CAR ARRAYS WITH IRREGULAR SIZED ENTRIES 审中-公开

    公开(公告)号：US20180210994A1

    公开(公告)日：2018-07-26

    申请号：US15416731

    申请日：2017-01-26

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John J. Wuu ,  Patrick J. Shyvers ,  Ryan Alan Selby

    IPC: G06F17/50 ,  G11C7/06 ,  G11C7/20

    CPC classification number: G06F17/5077 ,  G06F17/5072 ,  G06F17/5081 ,  G11C5/025 ,  G11C7/06 ,  G11C7/20

    Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. A memory macro block includes at least a primary array and a sidecar array. The primary array stores a first portion of a memory line and the sidecar array stores a second smaller portion of the memory line being accessed. The primary array and the sidecar array have different heights. The height of the sidecar array is based on a notch height in at least one corner of the memory macro block. The notch creates on-die space for s reserved area on the die. The notches result in cross-shaped, T-shaped, and/or L-shaped memory macro blocks.

    System and method for multiplexer tree indexing
    6.
    发明授权
    System and method for multiplexer tree indexing 有权

    公开(公告)号：US11308057B2

    公开(公告)日：2022-04-19

    申请号：US15824771

    申请日：2017-11-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Steven R. Havlir ,  Patrick J. Shyvers

    IPC: G06F16/22 ,  G06F9/38

    Abstract: Described herein is a system and method for multiplexer tree (muxtree) indexing. Muxtree indexing performs hashing and row reduction in parallel by use of each select bit only once in a particular path of the muxtree. The muxtree indexing generates a different final index as compared to conventional hashed indexing but still results in a fair hash, where all table entries get used with equal distribution with uniformly random selects.

    Encoded enable clock gaters
    8.
    发明授权
    Encoded enable clock gaters 有权

    公开(公告)号：US11776599B2

    公开(公告)日：2023-10-03

    申请号：US17485178

    申请日：2021-09-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Patrick J. Shyvers

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/106 ,  G11C7/1039 ,  G11C7/1087

    Abstract: A processing device is provided which includes a processor and a data storage structure. The data storage structure comprises a data storage array comprising a plurality of lines. Each line comprises at least one A latch configured to store a data bit and a clock gater. The data storage structure also comprises a write data B latch configured to store, over different clock cycles, a different data bit, each to be written to the at least one A latch of one of the plurality of lines. The data storage structure also comprises a plurality of write index B latches shared by the clock gaters of the lines. The write index B latches are configured to store, over the different clock cycles, combinations of index bits having values which index one of the lines to which a corresponding data bit is to be stored.

    DETERMINISTIC MIXED LATENCY CACHE
    9.
    发明申请
    DETERMINISTIC MIXED LATENCY CACHE 有权

    公开(公告)号：US20230101038A1

    公开(公告)日：2023-03-30

    申请号：US17489741

    申请日：2021-09-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Patrick J. Shyvers

    IPC: G06F12/0891 ,  G06F12/02 ,  G06F3/06 ,  G06F1/08

    Abstract: A method and processing device for accessing data is provided. The processing device comprises a cache and a processor. The cache comprises a first data section having a first cache hit latency and a second data section having a second cache hit latency that is different from the first cache hit latency of the first data section. The processor is configured to request access to data in memory, the data corresponding to a memory address which includes an identifier that identifies the first data section of the cache. The processor is also configured to load the requested data, determined to be located in the first data section of the cache, according to the first cache hit latency of the first data section of the cache.

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