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1.发明授权公开(公告)号：US09373418B2
公开(公告)日：2016-06-21
申请号：US14146118
申请日：2014-01-02
Applicant: Advanced Micro Devices, Inc.
Inventor： Russell Schreiber , Stephen Kosonocky , Amlan Ghosh
CPC classification number: G11C29/24 , G11C11/41 , G11C29/028 , G11C2029/0409 , G11C2029/1204
Abstract: A circuit with headroom monitoring includes a memory array having memory cells, a replica array, and a built-in self test circuit. The replica array has a plurality of word lines, a plurality of bit line pairs, and memory cells located at intersections of the plurality of word lines and the plurality of bit line pairs. The memory cells are of a same type as memory cells in the memory array. The built-in self test circuit is coupled to the replica array for adding a capacitance to at least one bit line of the plurality of bit line pairs, for sensing a read time of memory cells of the replica array with the capacitance so added, and for providing a headroom signal in response to the read time.
Abstract translation: 具有净空监测的电路包括具有存储单元的存储器阵列，复制阵列和内置自测电路。 复制数组具有多个字线，多个位线对和位于多个字线和多个位线对的交点处的存储单元。 存储单元与存储器阵列中的存储单元具有相同的类型。 内置的自检电路耦合到副本阵列，用于向多个位线对中的至少一个位线添加电容，用于利用所添加的电容感测副本阵列的存储器单元的读取时间;以及 用于响应于读取时间提供净空信号。
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公开(公告)号：US20150241955A1
公开(公告)日：2015-08-27
申请号：US14190803
申请日：2014-02-26
Applicant: Advanced Micro Devices, Inc.
Inventor： Stephen Kosonocky , Samuel Naffziger
CPC classification number: G06F1/3296 , G06F1/206 , G06F1/3206 , Y02D10/16 , Y02D10/172
Abstract: Some embodiments of a processing device include one or more power supply monitors to provide one or more counts representative of one or more operating frequencies of one or more circuit blocks based on a voltage supplied to the circuit block(s). Some embodiments of the processing device also include a system management unit to determine an initial voltage supplied to the circuit block(s) based on a target count and to reduce the voltage supplied to the circuit block(s) from the initial voltage in response to the count(s) generated by the power supply monitor(s) exceeding the target count.
Abstract translation: 处理装置的一些实施例包括一个或多个电源监视器，以基于提供给电路块的电压来提供表示一个或多个电路块的一个或多个工作频率的一个或多个计数。 处理装置的一些实施例还包括系统管理单元，用于基于目标计数确定提供给电路块的初始电压，并且响应于初始电压减小提供给电路块的电压与初始电压 电源监视器产生的计数超过目标计数。
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3.发明申请CIRCUIT AND DATA PROCESSOR WITH HEADROOM MONITORING AND METHOD THEREFOR 有权电路和数据处理器，具有HEADROOM监测及其方法公开(公告)号：US20150187437A1
公开(公告)日：2015-07-02
申请号：US14146118
申请日：2014-01-02
Applicant: Advanced Micro Devices, Inc.
Inventor： Russell Schreiber , Stephen Kosonocky , Amlan Ghosh
CPC classification number: G11C29/24 , G11C11/41 , G11C29/028 , G11C2029/0409 , G11C2029/1204
Abstract: A circuit with headroom monitoring includes a memory array having memory cells, a replica array, and a built-in self test circuit. The replica array has a plurality of word lines, a plurality of bit line pairs, and memory cells located at intersections of the plurality of word lines and the plurality of bit line pairs. The memory cells are of a same type as memory cells in the memory array. The built-in self test circuit is coupled to the replica array for adding a capacitance to at least one bit line of the plurality of bit line pairs, for sensing a read time of memory cells of the replica array with the capacitance so added, and for providing a headroom signal in response to the read time.
Abstract translation: 具有净空监测的电路包括具有存储单元的存储器阵列，复制阵列和内置自测电路。 复制数组具有多个字线，多个位线对和位于多个字线和多个位线对的交点处的存储单元。 存储单元与存储器阵列中的存储单元具有相同的类型。 内置的自检电路耦合到副本阵列，用于向多个位线对中的至少一个位线添加电容，用于利用所添加的电容感测副本阵列的存储器单元的读取时间;以及 用于响应于读取时间提供净空信号。
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公开(公告)号：US09772676B2
公开(公告)日：2017-09-26
申请号：US14190803
申请日：2014-02-26
Applicant: Advanced Micro Devices, Inc.
Inventor： Stephen Kosonocky , Samuel Naffziger
CPC classification number: G06F1/3296 , G06F1/206 , G06F1/3206 , Y02D10/16 , Y02D10/172
Abstract: Some embodiments of a processing device include one or more power supply monitors to provide one or more counts representative of one or more operating frequencies of one or more circuit blocks based on a voltage supplied to the circuit block(s). Some embodiments of the processing device also include a system management unit to determine an initial voltage supplied to the circuit block(s) based on a target count and to reduce the voltage supplied to the circuit block(s) from the initial voltage in response to the count(s) generated by the power supply monitor(s) exceeding the target count.
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