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    SEMICONDUCTOR PROCESSING DEVICE AND SEMICONDUCTOR PROCESSING SYSTEM
    1.
    发明申请
    SEMICONDUCTOR PROCESSING DEVICE AND SEMICONDUCTOR PROCESSING SYSTEM 审中-公开
    半导体处理器件和半导体处理系统

    公开(公告)号：US20130314147A1

    公开(公告)日：2013-11-28

    申请号：US13984875

    申请日：2012-03-28

    申请人： Nobuo Shimizu ,  Yutaka Takikawa

    发明人： Nobuo Shimizu ,  Yutaka Takikawa

    IPC分类号： H03M1/66

    CPC分类号： H03M1/66 ,  G06F1/22 ,  H03F3/2171

    摘要： A semiconductor processing device (10) of the present invention includes a processing circuit (1), a digital-analog conversion circuit (2), an output control circuit (3), at least one output port circuit (4), a connection control circuit (5), and an output switch circuit (6). The output port circuit (4) includes an output buffer (41), a first switch element (SW1), and a second switch element (SW2, SW3). When the second switch element is connected to the side of an output amplifier (42), the output port circuit (4) controls the ON resistance of a P channel MOS transistor (41a) and an N channel MOS transistor (41b) based on a signal amplified at the output amplifier (42) to output an analog signal from the output buffer (41).

    摘要翻译： 本发明的半导体处理装置（10）包括处理电路（1），数模转换电路（2），输出控制电路（3），至少一个输出端口电路（4），连接控制 电路（5）和输出开关电路（6）。 输出端口电路（4）包括输出缓冲器（41），第一开关元件（SW1）和第二开关元件（SW2，SW3）。 当第二开关元件连接到输出放大器（42）的一侧时，输出端口电路（4）基于一个P沟道MOS晶体管（41a）和N沟道MOS晶体管（41b）控制导通电阻 信号在输出放大器（42）处被放大，以从输出缓冲器（41）输出模拟信号。

    Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner
    4.
    发明授权
    Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner 有权
    具有集中布置缓冲器或保护电路的布局的半导体集成电路

    公开(公告)号：US07358548B2

    公开(公告)日：2008-04-15

    申请号：US11328194

    申请日：2006-01-10

    申请人： Tadashi Nakamura ,  Kiyohiko Sakakibara ,  Yutaka Takikawa

    发明人： Tadashi Nakamura ,  Kiyohiko Sakakibara ,  Yutaka Takikawa

    IPC分类号： H01L29/00 ,  H01L27/10

    CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/11898

    摘要： Buffers are arranged in a concentrated manner in a region distant from pads. The region refers to a region in a main region of a semiconductor integrated circuit, except for a central processing unit, a non-volatile memory and a volatile memory. As the buffer requiring a large area is not provided around the pad, a pitch between the pads or a pitch between the pad and an internal circuit (such as the central processing unit) can be made smaller and hence a chip size can be reduced. Therefore, a semiconductor integrated circuit capable of achieving a reduced chip size can be provided.

    摘要翻译： 缓冲器以集中的方式排列在远离焊盘的区域中。 该区域是指除了中央处理单元，非易失性存储器和易失性存储器之外的半导体集成电路的主要区域中的区域。 由于在焊盘周围不设置需要大面积的缓冲器，因此可以使焊盘之间的间距或焊盘与内部电路（例如中央处理单元）之间的间距更小，从而可以减小芯片尺寸。 因此，能够提供能够实现芯片尺寸减小的半导体集成电路。

    Phase-locked loop circuit with high lock speed and stability
    5.
    发明授权
    Phase-locked loop circuit with high lock speed and stability 失效
    具有高锁定速度和稳定性的锁相环电路

    公开(公告)号：US06392497B1

    公开(公告)日：2002-05-21

    申请号：US09761849

    申请日：2001-01-18

    申请人： Yutaka Takikawa

    发明人： Yutaka Takikawa

    IPC分类号： H03L708

    CPC分类号： H03L7/093 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/18

    摘要： A phase-locked loop circuit includes a voltage-controlled oscillator that includes a series circuit having a P-channel transistor, N-channel transistor, a third resistor and a first resistor connected in series in this order; a second resistor connected in parallel with a series circuit of the N-channel transistor and the third resistor; and an operational amplifier having its non-inverting input terminal connected to an output terminal of a lowpass filter, its inverting input terminal connected to a connected point of the third resistor and first resistor, and its output terminal connected to a gate of the N-channel transistor. The variable region of the resistance of the parallel circuit consisting of the N-channel transistor and the third and first resistors can be limited, which in turn enables the variable region of the control voltage of the voltage-controlled oscillator including a locking control voltage to be limited to a desired range. This makes it possible to limit the oscillation frequency of the voltage-controlled oscillator determined by the voltage signal fed from the lowpass filter to a desired range, and to increase its lock speed and stability at the same time.

    摘要翻译： 锁相环电路包括压控振荡器，其包括具有P沟道晶体管，N沟道晶体管，第三电阻器和第一电阻器的串联电路，该串联电路以该顺序串联连接; 与N沟道晶体管和第三电阻器的串联电路并联连接的第二电阻器; 以及运算放大器，其非反相输入端连接到低通滤波器的输出端，其反相输入端连接到第三电阻和第一电阻的连接点，其输出端连接到N- 通道晶体管。 可以限制由N沟道晶体管和第三和第一电阻组成的并联电路的电阻的可变区域，这进而使压控振荡器的控制电压的可变区域包括锁定控制电压 被限制在所需的范围内。 这使得可以将由从低通滤波器馈送的电压信号确定的压控振荡器的振荡频率限制到期望的范围，并且同时增加其锁定速度和稳定性。

    Semiconductor Memory
    6.
    发明申请
    Semiconductor Memory 失效
    半导体存储器

    公开(公告)号：US20090059665A1

    公开(公告)日：2009-03-05

    申请号：US12266421

    申请日：2008-11-06

    申请人： Yutaka Takikawa ,  Koichi Kawauchi ,  Satoko Kamakura ,  Kazuo Nomura ,  Kazuyuki Kawamoto ,  Nobutaka Imanishi

    发明人： Yutaka Takikawa ,  Koichi Kawauchi ,  Satoko Kamakura ,  Kazuo Nomura ,  Kazuyuki Kawamoto ,  Nobutaka Imanishi

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： H01L27/11521 ,  G11C7/18 ,  G11C16/0433 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524

    摘要： A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.

    摘要翻译： 实现了半导体存储器，其允许减少存储器阵列块的面积而不减小浮动栅极的栅极宽度。 多个选择门在X方向上以直线延伸。 在上下选择门之间，排列有两行的浮动门。 多个浮动门以交错布置（换句话说，以之字形模式）放置。 也就是说，在特定列中的一个浮动栅极和与该特定列相邻的列中的另一个浮动栅极，那些浮动栅极在Y方向上彼此偏离。

    Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner
    7.
    发明申请
    Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner 有权
    具有集中布置缓冲器或保护电路的布局的半导体集成电路

    公开(公告)号：US20060163615A1

    公开(公告)日：2006-07-27

    申请号：US11328194

    申请日：2006-01-10

    申请人： Tadashi Nakamura ,  Kiyohiko Sakakibara ,  Yutaka Takikawa

    发明人： Tadashi Nakamura ,  Kiyohiko Sakakibara ,  Yutaka Takikawa

    IPC分类号： H01L27/10

    CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/11898

    摘要： Buffers are arranged in a concentrated manner in a region distant from pads. The region refers to a region in a main region of a semiconductor integrated circuit, except for a central processing unit, a non-volatile memory and a volatile memory. As the buffer requiring a large area is not provided around the pad, a pitch between the pads or a pitch between the pad and an internal circuit (such as the central processing unit) can be made smaller and hence a chip size can be reduced. Therefore, a semiconductor integrated circuit capable of achieving a reduced chip size can be provided.

    摘要翻译： 缓冲器以集中的方式排列在远离焊盘的区域中。 该区域是指除了中央处理单元，非易失性存储器和易失性存储器之外的半导体集成电路的主要区域中的区域。 由于在焊盘周围不设置需要大面积的缓冲器，因此可以使焊盘之间的间距或焊盘与内部电路（例如中央处理单元）之间的间距更小，从而可以减小芯片尺寸。 因此，能够提供能够实现芯片尺寸减小的半导体集成电路。

    Phase-locked loop circuit with charge pump and time constant circuit
    8.
    发明授权
    Phase-locked loop circuit with charge pump and time constant circuit 失效
    带电荷泵和时间常数电路的锁相环电路

    公开(公告)号：US5912575A

    公开(公告)日：1999-06-15

    申请号：US807086

    申请日：1997-02-27

    申请人： Yutaka Takikawa

    发明人： Yutaka Takikawa

    IPC分类号： H03L7/093 ,  H03L7/089 ,  H03L7/10 ,  H03L7/06

    CPC分类号： H03L7/0898

    摘要： A phase-locked loop (PLL) circuit includes a low-pass filter, a voltage controlled oscillator that produces a PLL signal having a frequency that differs according to a control voltage supplied by the low-pass filter, a phase detector which receives the PLL signal and a reference signal and detects a phase difference between them to produce an error signal, and a charge pump that, in response to the error signal, supplies a charge to the low-pass filter or extracts a charge from the low-pass filter. The charge pump includes a variable resistance element the resistance of which varies when the error signal is applied, thereby nonlinearly adjusting the charge supplied to or extracted from the low-pass filter with respect to the duration of the error signal from the phase detector.

    摘要翻译： 锁相环（PLL）电路包括低通滤波器，产生具有根据由低通滤波器提供的控制电压而不同的频率的PLL信号的压控振荡器，接收PLL的相位检测器 信号和参考信号，并检测它们之间的相位差以产生误差信号;以及电荷泵，其响应于误差信号向低通滤波器提供电荷或从低通滤波器提取电荷 。 电荷泵包括可变电阻元件，其电阻在施加误差信号时变化，从而相对于来自相位检测器的误差信号的持续时间非线性地调节从低通滤波器提供或从低通滤波器提取的电荷。