公开(公告)号：US08680686B2

公开(公告)日：2014-03-25

申请号：US12826366

申请日：2010-06-29

Applicant: Lai Nguk Chin ,  Foong Yue Ho ,  Wong Kwet Nam ,  Thor Lee Lee ,  Sally Foong ,  Kevin Guan

Inventor： Lai Nguk Chin ,  Foong Yue Ho ,  Wong Kwet Nam ,  Thor Lee Lee ,  Sally Foong ,  Kevin Guan

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/00014 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665

Abstract: A system and method for a thin multi chip stack package with film on wire and copper wire. The package comprises a substrate and a first die overlying the substrate. Copper wires electrically connect the first die to the substrate. A film overlies the first die and a portion of the copper wires. In addition, the film adheres a second die to the first die. The film also electrically insulates the copper wires from the second die.

Abstract translation: 一种薄的多芯片堆叠封装的系统和方法，薄膜在线和铜线上。 该封装包括衬底和覆盖衬底的第一裸片。 铜线将第一芯片与基板电连接。 一层薄膜覆盖在第一模具和铜线的一部分之间。 此外，膜将第二模具粘附到第一模具。 该薄膜还使铜线与第二模具电绝缘。

公开(公告)号：US20110316158A1

公开(公告)日：2011-12-29

申请号：US12826366

申请日：2010-06-29

Applicant: Lai Nguk CHIN ,  Foong Yue HO ,  Wong Kwet NAM ,  Thor Lee LEE ,  Sally FOONG ,  Kevin GUAN

Inventor： Lai Nguk CHIN ,  Foong Yue HO ,  Wong Kwet NAM ,  Thor Lee LEE ,  Sally FOONG ,  Kevin GUAN

IPC: H01L25/065 ,  H01L21/60 ,  H01L23/52

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/00014 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665

Abstract: A system and method for a thin multi chip stack package with film on wire and copper wire. The package comprises a substrate and a first die overlying the substrate. Copper wires electrically connect the first die to the substrate. A film overlies the first die and a portion of the copper wires. In addition, the film adheres a second die to the first die. The film also electrically insulates the copper wires from the second die.

Abstract translation: 一种薄的多芯片堆叠封装的系统和方法，薄膜在线和铜线上。 该封装包括衬底和覆盖衬底的第一裸片。 铜线将第一芯片与基板电连接。 一层薄膜覆盖在第一模具和铜线的一部分之间。 此外，膜将第二模具粘附到第一模具。 该薄膜还使铜线与第二模具电绝缘。

公开(公告)号：US20120038059A1

公开(公告)日：2012-02-16

申请号：US12853856

申请日：2010-08-10

Applicant: Lai Nguk CHIN ,  Foong Yue HO ,  Wong Kwet NAM ,  Koo Eng LUON ,  Sally FOONG ,  Kevin GUAN

Inventor： Lai Nguk CHIN ,  Foong Yue HO ,  Wong Kwet NAM ,  Koo Eng LUON ,  Sally FOONG ,  Kevin GUAN

IPC: H01L23/49 ,  H01L21/50

CPC classification number: H01L24/49 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48456 ,  H01L2224/48465 ,  H01L2224/4848 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48997 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49427 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/8503 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85951 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48455 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

Abstract translation: 公开了一种用于芯片堆叠的方法。 在一个实施例中，第一管芯形成在衬底上。 第一线被接合到第一管芯和衬底的接合指状物，其中第一电线用第一接合键合到接合指状物。 第一缝合凸起形成在第一线圈接合之上，其中第一线圈凸起由导电材料的熔融球形成。 第二模具形成在第一模具上方。 第二线被接合到第二模具和第一线圈凸块，其中第二线材以第二接合键合到第一线圈凸块。

公开(公告)号：US07799612B2

公开(公告)日：2010-09-21

申请号：US11767623

申请日：2007-06-25

Applicant: Sally Foong ,  Tan Kiah Ling ,  Kee Cheng Sim ,  Wong Kwet Nam ,  Yue Ho Foong

Inventor： Sally Foong ,  Tan Kiah Ling ,  Kee Cheng Sim ,  Wong Kwet Nam ,  Yue Ho Foong

IPC: H01L21/00

CPC classification number: H01L24/83 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L2221/6834 ,  H01L2224/2919 ,  H01L2224/743 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00

Abstract: Methods and systems of applying a plurality of pieces of die attach film to a plurality of singulated dice are provided. The method can involve making intervals between rows and columns of a plurality of pieces of die attach film. The interval can be made by expanding an underlaid expandable film on which the plurality of pieces of die attach film are placed or by removing portions of the die attach film between rows and columns of the plurality of pieces of die attach film. The method can further involve placing a plurality of singulated dice back side down on the plurality of pieces of die attach film.

Abstract translation: 提供了将多个芯片附着膜施加到多个单个裸片上的方法和系统。 该方法可以包括在多个芯片附着膜的行和列之间进行间隔。 间隔可以通过扩大其上放置有多个管芯附着膜的底层可膨胀膜，或者通过在多个芯片附着膜的行和列之间去除芯片附着膜的一部分来进行。 该方法还可以包括将多个分割的骰子背面放置在多个贴片膜上。

公开(公告)号：US08357563B2

公开(公告)日：2013-01-22

申请号：US12853856

申请日：2010-08-10

Applicant: Lai Nguk Chin ,  Foong Yue Ho ,  Wong Kwet Nam ,  Koo Eng Luon ,  Sally Foong ,  Kevin Guan

Inventor： Lai Nguk Chin ,  Foong Yue Ho ,  Wong Kwet Nam ,  Koo Eng Luon ,  Sally Foong ,  Kevin Guan

IPC: H01L21/00

CPC classification number: H01L24/49 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48456 ,  H01L2224/48465 ,  H01L2224/4848 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48997 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49427 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/8503 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85951 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48455 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

Abstract translation: 公开了一种用于芯片堆叠的方法。 在一个实施例中，第一管芯形成在衬底上。 第一线被接合到第一管芯和衬底的接合指状物，其中第一电线用第一接合键合到接合指状物。 第一缝合凸起形成在第一线圈接合之上，其中第一线圈凸起由导电材料的熔融球形成。 第二模具形成在第一模具上方。 第二线被接合到第二模具和第一线圈凸块，其中第二线材以第二接合键合到第一线圈凸块。

公开(公告)号：US07157376B1

公开(公告)日：2007-01-02

申请号：US10918395

申请日：2004-08-16

Applicant: Sally Y. L. Foong ,  Lim See-Kee ,  Wong Kwet Nam

Inventor： Sally Y. L. Foong ,  Lim See-Kee ,  Wong Kwet Nam

IPC: H01L21/302

CPC classification number: H01L21/02008 ,  H01L21/3065 ,  H01L21/6732 ,  Y10T29/41

Abstract: Cassettes for holding thin semiconductor wafers for safe handling are provided, along with an improved methodology for reducing the thickness of semiconductor wafers. Embodiments include a cassette for holding thin semiconductor wafers, having a plurality of sets of center and edge supports, the sets being spaced from each other a distance greater than a sag amount of the wafers. The thin wafers are supported in a predetermined reference plane, so that tools such as robots or automatic handlers can be programmed to pick them up without damaging them. In another embodiment, a double into single pitch wafer cassette is provided having a wafer entrance section with spacing twice as large between sets of edge supports as a conventional cassette, to accommodate the sag/warp of the thin wafers, and a “flattening section” which guides and flattens the wafers between opposing edge supports as they are pushed into the cassette, such that the wafers are held substantially planar. Because the wafers are held substantially planar, they can be safely removed from the cassette by automatic tools. A methodology is also provided for reducing the thickness of a semiconductor wafer, comprising grinding the back side of the wafer to reduce its initial thickness to an intermediate thickness, and plasma etching the back side of the wafer to reduce the intermediate thickness to a final thickness. The two-step grinding/etching process is faster and less expensive than conventional multi-step grinding/polishing processes, because it requires less steps, each step is accomplished relatively quickly, and it employs standard grinding and etching equipment, rather than expensive dedicated equipment.

Abstract translation: 提供了用于保持用于安全处理的薄半导体晶片的盒，以及用于减小半导体晶片的厚度的改进的方法。 实施例包括用于保持薄半导体晶片的盒，具有多组中心和边缘支撑件，所述组彼此间隔开大于晶片下垂量的距离。 薄晶片被支撑在预定的参考平面中，使得诸如机器人或自动处理器的工具可以被编程以拾取它们而不损坏它们。 在另一个实施例中，提供双进单节距晶片盒，其具有晶片入口部分，其在传统盒体之间的边缘支撑件之间具有间隔两倍的距离，以适应薄晶片的松弛/翘曲，以及“扁平部分” 当它们被推入盒中时，它们在相对边缘支撑件之间引导和平坦化晶片，使得晶片保持基本上平面。 因为晶片被保持为基本上平面的，它们可以通过自动工具被安全地从盒中移除。 还提供了一种用于减小半导体晶片的厚度的方法，包括研磨晶片的背面以将其初始厚度减小到中间厚度，以及等离子体蚀刻晶片的背面以将中间厚度减小到最终厚度 。 两步磨削/蚀刻工艺比传统的多步磨削/抛光工艺更快，更便宜，因为它需要更少的步骤，每个步骤都相对较快地完成，并且采用标准的研磨和蚀刻设备，而不是昂贵的专用设备 。