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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US07016238B2

    公开(公告)日：2006-03-21

    申请号：US11055969

    申请日：2005-02-14

    申请人： Hiroshi Shimizu ,  Wataru Yokozeki

    发明人： Hiroshi Shimizu ,  Wataru Yokozeki

    IPC分类号： G11C7/00

    CPC分类号： G11C11/413 ,  G11C7/18 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C11/418

    摘要： A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the ON state to select one of local blocks arranged in a column direction. A NAND element inverts the logical product of a signal output from a local block selected by a local block selection signal and a signal output from a block not selected and outputs a result obtained to put an n-channel transistor into the ON or OFF state. The n-channel transistor grounds a common bit line when it goes into the ON state. Each of the p-channel transistors is selected by a column switch (not shown) and send read data to a data bus.

    Semiconductor integrated circuit
    2.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US07002834B2

    公开(公告)日：2006-02-21

    申请号：US10778320

    申请日：2004-02-17

    申请人： Wataru Yokozeki

    发明人： Wataru Yokozeki

    IPC分类号： G11C11/22

    CPC分类号： G11C5/14 ,  G11C11/22

    摘要： At switching normal operation mode to low power mode, a first switch disconnects a virtual power supply line and a normal power supply line in response to activation of a switch control signal. The power supply voltage to a first circuit block connected to the virtual power supply line is suspended during the low power mode. A second switch of a floating prevention circuit connects a node between output of the first circuit block and input of a second circuit block to a first voltage line in response to inactivation of the switch control signal during the low power mode. This prevents the input of the second circuit block from floating even without the power supply voltage supplied to the first circuit block, and therefore prevents feedthrough current from flowing through the second circuit block, which enables reduction in power consumption during the low power mode.

    摘要翻译： 在将正常操作模式切换到低功率模式时，第一开关响应于开关控制信号的激活而断开虚拟电源线和正常电源线。 连接到虚拟电源线的第一电路块的电源电压在低功率模式期间被暂停。 浮动防止电路的第二开关响应于低功率模式期间开关控制信号的失活，将第一电路块的输出和第二电路块的输入之间的节点连接到第一电压线。 即使没有提供给第一电路块的电源电压，也可防止第二电路块的输入浮动，并且因此防止馈通电流流过第二电路块，这能够在低功率模式期间降低功耗。

    Semiconductor device, a method of manufacturing the semiconductor device and a method of deleting information from the semiconductor device
    4.
    发明授权
    Semiconductor device, a method of manufacturing the semiconductor device and a method of deleting information from the semiconductor device 失效
    半导体器件，半导体器件的制造方法和从半导体器件中删除信息的方法

    公开(公告)号：US06917076B2

    公开(公告)日：2005-07-12

    申请号：US10630833

    申请日：2003-07-31

    申请人： Kohei Eguchi ,  Yuichi Egawa ,  Shoichi Iwasa ,  Hideki Fujikake ,  Wataru Yokozeki ,  Tatsuya Kawamata

    发明人： Kohei Eguchi ,  Yuichi Egawa ,  Shoichi Iwasa ,  Hideki Fujikake ,  Wataru Yokozeki ,  Tatsuya Kawamata

    IPC分类号： H01L21/761 ,  H01L21/765 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/115 ,  H01L27/148 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L27/11521 ,  H01L21/761 ,  H01L21/765 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1463

    摘要： A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOCOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure. After gate electrode wiring layers are formed in a field region and an active region to the same level, a pad polysilicon film formed on the entire surface to cover the patterns of these gate electrode wiring layers is polished by chemical mechanical polishing (CMP) using the cap insulating films of the gate electrode wiring layers as stoppers, thereby forming the gate electrode wiring layers into separated patterns. With this arrangement, even when the width of the gate electrode wiring layer is reduced to the exposure limit in photolithography, the pad polysilicon film can be separated and patterned.

    摘要翻译： 半导体器件及其制造方法以及使用半导体器件的信息的删除方法，其中使用场屏蔽隔离或元件之间的沟槽型隔离，同时抑制场氧化物穿透到器件的有源区域 ，也就是说，涉及常规LOCOS型工艺的缺陷。 在半导体衬底中形成非LOCOS绝缘器件隔离块。 非LOCOS绝缘器件隔离块使用场屏蔽元件隔离结构或沟槽型元件隔离结构。 在场区域和有源区域中形成相同电平的栅极电极布线层之后，通过化学机械抛光（CMP）对形成在覆盖这些栅极布线层的图案的整个表面上的焊盘多晶硅膜进行抛光 将栅电极配线层的绝缘膜作为止动器，由此将栅电极配线层形成分离图案。 利用这种布置，即使在光刻中将栅极布线层的宽度减小到曝光极限时，也可以分离和图案化衬垫多晶硅膜。

    Semiconductor memory having a plurality of word lines shared by adjacent local block
    5.
    发明授权
    Semiconductor memory having a plurality of word lines shared by adjacent local block 有权
    具有由相邻的本地块共享的多个字线的半导体存储器

    公开(公告)号：US06870788B2

    公开(公告)日：2005-03-22

    申请号：US10199070

    申请日：2002-07-22

    申请人： Hiroshi Shimizu ,  Wataru Yokozeki

    发明人： Hiroshi Shimizu ,  Wataru Yokozeki

    IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C8/10 ,  G11C8/12 ,  G11C11/407 ,  G11C11/409 ,  G11C11/41 ,  G11C11/418 ,  G11C8/00

    CPC分类号： G11C11/413 ,  G11C7/18 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C11/418

    摘要： A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the ON state to select one of local blocks arranged in a column direction. A NAND element inverts the logical product of a signal output from a local block selected by a local block selection signal and a signal output from a block not selected and outputs a result obtained to put an n-channel transistor into the ON or OFF state. The n-channel transistor grounds a common bit line when it goes into the ON state. Each of the p-channel transistors is selected by a column switch (not shown) and send read data to a data bus.

    摘要翻译： 一种加速其操作的半导体存储器件。 多路复用器将字线中的一条置于活动状态，以选择每个局部块中的一个存储单元。 另一个多路复用器将局部块选择信号中的一个置入活动状态，并将p沟道晶体管中的一个置于ON状态，以选择沿列方向布置的一个局部块。 NAND元件将由本地块选择信号选择的本地块输出的信号和未被选择的块输出的信号的逻辑积反相，并输出将n沟道晶体管置于ON或OFF状态所得到的结果。 当n沟道晶体管进入ON状态时，接地公共位线。 通过列开关（未示出）选择每个p沟道晶体管，并将读数据发送到数据总线。

    Semiconductor memory
    6.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US06741487B2

    公开(公告)日：2004-05-25

    申请号：US10202855

    申请日：2002-07-26

    申请人： Wataru Yokozeki

    发明人： Wataru Yokozeki

    IPC分类号： G11C506

    CPC分类号： G11C8/12

    摘要： A semiconductor memory that reduces the amount of power consumed by an entire unit by decreasing a charging/discharging current. A row direction selection circuit selects predetermined memory cell groups in a row direction in response to a row input address signal. A column direction selection circuit selects predetermined memory cell groups in a column direction in response to a column input address signal. Connection-disconnection circuits connect a divided bit line corresponding to a column selected by the column direction selection circuit of divided bit lines connected to memory cell groups, respectively, selected by the row direction selection circuit to the corresponding common bit line and do not connect divided bit lines corresponding to the other columns.

    摘要翻译： 一种半导体存储器，其通过减少充电/放电电流来减少整个单元消耗的功率量。 行方向选择电路响应于行输入地址信号而选择行方​​向上的预定存储单元组。 列方向选择电路响应于列输入地址信号在列方向上选择预定的存储单元组。 连接断开电路将与行存储单元组连接的划分的位线的列方向选择电路选择的列对应的划分的位线分别连接到相应的公共位线，并且不连接分开 对应于其他列的位线。

    Semiconductor memory device
    7.
    发明申请
    Semiconductor memory device 有权

    公开(公告)号：US20070247956A1

    公开(公告)日：2007-10-25

    申请号：US11812144

    申请日：2007-06-15

    申请人： Hiroshi Shimizu ,  Wataru Yokozeki

    发明人： Hiroshi Shimizu ,  Wataru Yokozeki

    IPC分类号： G11C8/00

    CPC分类号： G11C11/413 ,  G11C7/18 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C11/418

    摘要： A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the ON state to select one of local blocks arranged in a column direction. A NAND element inverts the logical product of a signal output from a local block selected by a local block selection signal and a signal output from a block not selected and outputs a result obtained to put an n-channel transistor into the ON or OFF state. The n-channel transistor grounds a common bit line when it goes into the ON state. Each of the p-channel transistors is selected by a column switch (not shown) and send read data to a data bus.

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07248534B2

    公开(公告)日：2007-07-24

    申请号：US11312586

    申请日：2005-12-21

    申请人： Hiroshi Shimizu ,  Wataru Yokozeki

    发明人： Hiroshi Shimizu ,  Wataru Yokozeki

    IPC分类号： G11C8/00

    CPC分类号： G11C11/413 ,  G11C7/18 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C11/418

    摘要： A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the ON state to select one of local blocks arranged in a column direction. A NAND element inverts the logical product of a signal output from a local block selected by a local block selection signal and a signal output from a block not selected and outputs a result obtained to put an n-channel transistor into the ON or OFF state. The n-channel transistor grounds a common bit line when it goes into the ON state. Each of the p-channel transistors is selected by a column switch (not shown) and send read data to a data bus.

    摘要翻译： 一种加速其操作的半导体存储器件。 多路复用器将字线中的一条置于活动状态，以选择每个局部块中的一个存储单元。 另一个多路复用器将局部块选择信号中的一个置入活动状态，并将p沟道晶体管中的一个置于ON状态，以选择沿列方向布置的一个局部块。 NAND元件将由本地块选择信号选择的本地块输出的信号和未被选择的块输出的信号的逻辑积反相，并输出将n沟道晶体管置于ON或OFF状态所得到的结果。 当n沟道晶体管进入ON状态时，接地公共位线。 通过列开关（未示出）选择每个p沟道晶体管，并将读数据发送到数据总线。

    Digital PLL circuit
    9.
    发明申请
    Digital PLL circuit 有权

    公开(公告)号：US20060001464A1

    公开(公告)日：2006-01-05

    申请号：US11216166

    申请日：2005-09-01

    申请人： Wataru Yokozeki

    发明人： Wataru Yokozeki

    IPC分类号： H03L7/06

    CPC分类号： H03L7/07 ,  H03L7/0814 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0996 ,  H03L7/113 ,  H03L2207/50

    摘要： A frequency comparator compares frequencies of a reference clock and an output clock to output a frequency comparison signal. A frequency variable circuit is composed of a delay circuit, which has a plurality of inverting circuits connected in series, and a first selection circuit. The first selection circuit selects one of odd output signals outputted from odd-numbered inverting circuits, according to the frequency comparison signal to feedback the selected odd output signal to an input of the delay circuit as a feedback signal. A phase comparator compares phases of the reference clock and the output clock to output a phase comparison signal. A second selection circuit selects one of the odd output signals according to the phase comparison signal to output it as the output clock.

    Programmable logic device with ferroelectric configuration memories
    10.
    发明授权
    Programmable logic device with ferroelectric configuration memories 失效
    具有铁电配置存储器的可编程逻辑器件

    公开(公告)号：US06924663B2

    公开(公告)日：2005-08-02

    申请号：US10327653

    申请日：2002-12-24

    申请人： Shoichi Masui ,  Michiya Oura ,  Tsuzumi Ninomiya ,  Wataru Yokozeki ,  Kenji Mukaida

    发明人： Shoichi Masui ,  Michiya Oura ,  Tsuzumi Ninomiya ,  Wataru Yokozeki ,  Kenji Mukaida

    IPC分类号： G06F21/76 ,  G06F21/79 ,  G11C8/20 ,  H03K19/177 ,  H03K19/173 ,  G11C7/00

    CPC分类号： G06F21/76 ,  G06F21/79 ,  G11C8/20 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/1776 ,  H03K19/17768 ,  H03K19/17772 ,  H03K19/17776 ,  H03K19/1778

    摘要： A programmable logic device with ferroelectric configuration memories storing multiple configuration data sets. The device has programmable logic blocks, interconnections, and I/O blocks to provide desired logic functions. Those building blocks can be dynamically reconfigured by changing the selection of configuration data stored in the device's integral configuration memories. The configuration memories are divided into groups, so that they can be loaded concurrently with multiple configuration data streams. To protect the content of configuration memories from unauthorized access, the device employs an authentication mechanism that uses security IDs stored in the configuration memories. The device has a memory controller to provide an appropriate power supply sequence for ferroelectric memory cells to ensure the reliable data retention when the device is powered up or shut down.

    摘要翻译： 具有存储多个配置数据集的铁电配置存储器的可编程逻辑器件。 该器件具有可编程逻辑块，互连和I / O块，以提供所需的逻辑功能。 可以通过改变存储在设备的整体配置存储器中的配置数据的选择来动态地重构这些构建块。 配置存储器被分成组，使得它们可以与多个配置数据流同时加载。 为了保护配置存储器的内容免受未经授权的访问，设备采用使用存储在配置存储器中的安全ID的认证机制。 该器件具有存储器控制器，以为铁电存储器单元提供适当的电源序列，以确保在器件上电或关闭时可靠的数据保持。