公开(公告)号：US06657229B1

公开(公告)日：2003-12-02

申请号：US09379802

申请日：1999-08-24

申请人： Kohei Eguchi ,  Yuichi Egawa ,  Shoichi Iwasa ,  Hideki Fujikake ,  Wataru Yokozeki ,  Tatsuya Kawamata

发明人： Kohei Eguchi ,  Yuichi Egawa ,  Shoichi Iwasa ,  Hideki Fujikake ,  Wataru Yokozeki ,  Tatsuya Kawamata

IPC分类号： H01L2976

CPC分类号： H01L27/11521 ,  H01L21/761 ,  H01L21/765 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1463

摘要： A semiconductor device has field shield isolation or trench type isolation between elements which suppresses penetration of field oxide into an element active region of the device. A common gate is located between two MOS transistors, which may be of opposite conductivity type. After gate electrode wiring layers are formed in a field region and an active region to the same level, a pad polysilicon film formed on the entire surface to cover the patterns of these gate electrode wiring layers, which are in separated patterns.

摘要翻译： 半导体器件在元件之间具有场屏蔽隔离或沟槽型隔离，其抑制场氧化物穿透到器件的元件有源区域。 公共栅极位于两个MOS晶体管之间，其可以具有相反的导电类型。 在栅电极布线层形成在相同电平的场区域和有源区中之后，形成在整个表面上以覆盖这些栅电极布线层的图案的焊盘多晶硅膜，它们是分离的图案。

公开(公告)号：US6124638A

公开(公告)日：2000-09-26

申请号：US960257

申请日：1997-10-29

申请人： Shoichi Iwasa

发明人： Shoichi Iwasa

IPC分类号： H01L21/8242 ,  H01L29/72

CPC分类号： H01L27/10885 ,  H01L27/10894 ,  H01L27/10852

摘要： A polycide wiring layer constituted by a polysilicon film and a silicide film is used as a bit line of a DRAM. When a memory cell region having an n-type impurity diffusion layer and a peripheral circuit region having a p-type impurity diffusion layer are to be electrically connected through the polysilicon film, a diffusion prevention film consisting of TiSiN or WSiN is formed as an underlying film of the polysilicon film. With this diffusion prevention film, interdiffusion between the n- and p-type impurity diffusion layers can be prevented. In addition, heat resistance at 900.degree. C. or more can be obtained in processes after formation of the diffusion prevention film.

摘要翻译： 作为DRAM的位线，使用由多晶硅膜和硅化物膜构成的多晶硅布线层。 当具有n型杂质扩散层的存储单元区域和具有p型杂质扩散层的外围电路区域通过多晶硅膜电连接时，形成由TiSiN或WSiN组成的防扩散膜作为基础 多晶硅薄膜。 利用该扩散防止膜，可以防止n型和p型杂质扩散层之间的相互扩散。 此外，在形成扩散防止膜之后的工艺中可以获得在900℃以上的耐热性。

公开(公告)号：US5959319A

公开(公告)日：1999-09-28

申请号：US631682

申请日：1996-04-16

申请人： Shoichi Iwasa

发明人： Shoichi Iwasa

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： A semiconductor memory device has word line conductor films, bit line conductor films transverse to the word line conductor films and memory cells provided at intersections between the word line conductor films and bit line conductor films. Each memory cell has a transistor structure formed at a surface portion of a semiconductor substrate and a capacitor structure formed over the semiconductor substrate. The word line conductor films are formed at a level lower than the capacitor structures of the memory cells to improve the resolution of patterns for the semiconductor memory device.

公开(公告)号：US5747845A

公开(公告)日：1998-05-05

申请号：US700082

申请日：1996-08-20

申请人： Shoichi Iwasa

发明人： Shoichi Iwasa

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L27/08 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： A semiconductor memory device comprises a plurality of memory cells on a semiconductor substrate, each including a transistor with a pair of impurity diffusion layers and a gate electrode, and a capacitor, a first insulating film covering the transistors, a plurality of parallel extending word lines formed on the substrate, each being connected to the gate electrode of the transistor of at least one selected memory cell, a plurality of bit lines, each connected to one of the pair of impurity diffusion layers of at least one selected memory cell through a first contact hole in the first insulating layer, each bit line formed with a conductive film on a top surface thereof and a second insulating film interposed therebetween, a lower electrode of the capacitor at a predetermined position on the first insulating film electrically connected to one of the bit lines and to the other of the pair of impurity diffusion layers through a second contact hole formed in the first insulating film, wherein the conductive film on the top surface of each of the bit lines is formed by a material having an etching rate lower than that of the first insulating film in etching the first insulating film for the second contact hole.

摘要翻译： 半导体存储器件包括半导体衬底上的多个存储单元，每个存储单元包括具有一对杂质扩散层和栅电极的晶体管，以及电容器，覆盖晶体管的第一绝缘膜，多个平行延伸字线 形成在基板上，每个连接到至少一个所选择的存储单元的晶体管的栅电极，多个位线，每个位线通过第一个存储单元连接到至少一个选择的存储单元的一对杂质扩散层中的一个 所述第一绝缘层中的接触孔，其每个位线在其顶表面上形成有导电膜，并且在其间插入第二绝缘膜，所述电容器的下电极在所述第一绝缘膜上的预定位置处电连接到 通过形成在第一绝缘膜中的第二接触孔，一对杂质扩散层中的另一个杂质扩散层 通过在蚀刻用于第二接触孔的第一绝缘膜的蚀刻速率低于第一绝缘膜的蚀刻速率的材料形成每个位线的顶表面上的导电膜的材料。

公开(公告)号：US5424978A

公开(公告)日：1995-06-13

申请号：US212737

申请日：1994-03-14

申请人： Toshio Wada ,  Kenji Anzai ,  Shoichi Iwasa ,  Yasuo Sato ,  Yuichi Egawa

发明人： Toshio Wada ,  Kenji Anzai ,  Shoichi Iwasa ,  Yasuo Sato ,  Yuichi Egawa

IPC分类号： G11C11/56 ,  G11C11/34

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5634

摘要： A non-volatile semiconductor memory device capable of selectively storing one of at least three different data comprises a memory array including a plurality of memory cells, each having a control gate, a floating gate, a drain, and a source, a circuit for producing a stepped voltage whose level is varied stepwise to a number of different levels corresponding to a number of data to be stored, a circuit for producing a pulse voltage having a predetermined voltage level and a predetermined pulse width, and a circuit for selecting one of the plurality of memory cells, wherein during storing of the at least three different data the stepped voltage and the pulse voltage are applied to the control gate and the drain of the selected memory cell, respectively, while a timing of application of the pulse voltage to the drain is controlled relative to a timing of application of the stepped voltage to the control gate, depending on which of the at least three different data is to be stored into the selected memory cell.

摘要翻译： 能够选择性地存储至少三种不同数据中的一种的非易失性半导体存储器件包括：存储器阵列，其包括多个存储单元，每个存储单元具有控制栅极，浮置栅极，漏极和源极， 阶梯电压，其电平逐步变化为对应于要存储的数据的数量的不同电平的数量，用于产生具有预定电压电平和预定脉冲宽度的脉冲电压的电路，以及用于选择 多个存储单元，其中在存储所述至少三个不同数据期间，分阶段电压和脉冲电压分别施加到所选择的存储单元的控制栅极和漏极，同时将脉冲电压施加到 相对于将步进电压施加到控制栅极的时序来控制漏极，这取决于至少三个不同数据中的哪一个将被存储到第 e选择的存储单元。

公开(公告)号：US5381028A

公开(公告)日：1995-01-10

申请号：US183852

申请日：1994-01-21

申请人： Shoichi Iwasa

发明人： Shoichi Iwasa

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

CPC分类号： H01L29/66825 ,  H01L29/7883 ,  H01L27/115

摘要： The MOS field-effect transistor has a semiconductor substrate of a first conductivity type, a pair of first polycrystalline silicon layers of a second conductivity type different from the first conductivity type which are formed on the semiconductor substrate and separated from each other by a small gap, a pair of diffusion layers of the second conductivity type formed in those regions of the semiconductor substrate which are in contact with the pair of first polycrystalline silicon layers, respectively, a gate insulating film formed to cover the pair of first polycrystalline silicon layers of the second conductivity type and a part of the semiconductor substrate exposed to an outside at the small gap, and a gate electrode formed on the gate insulating film. The nonvolatile semiconductor memory device is arranged by using the MOS field-effect transistor mentioned above.

摘要翻译： MOS场效应晶体管具有第一导电类型的半导体衬底，不同于第一导电类型的第二导电类型的一对第一多晶硅层，其形成在半导体衬底上并且以小间隙彼此分离 分别形成在所述半导体衬底的与所述一对第一多晶硅层接触的区域中的一对第二导电类型的扩散层，形成为覆盖所述一对第一多晶硅层的栅极绝缘膜 第二导电类型和在小间隙暴露于外部的半导体衬底的一部分，以及形成在栅极绝缘膜上的栅电极。 通过使用上述的MOS场效应晶体管来配置非易失性半导体存储器件。

公开(公告)号：US5042008A

公开(公告)日：1991-08-20

申请号：US509892

申请日：1990-04-16

申请人： Shoichi Iwasa ,  Masaru Ohki

发明人： Shoichi Iwasa ,  Masaru Ohki

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7883 ,  H01L27/115 ,  H01L29/7881

摘要： A non-volatile memory device is fabricated on a semiconductor substrate structure and comprises a word line formed by a buried layer in the semiconductor substrate structure and a plurality of memory cells associated with the word line, and each of the memory cells comprises a control gate region of formed in the semiconductor substrate structure and extending from the word line to a major surface portion of the semiconductor substrate structure, a first gate insulating film covering a top surface of the control gate region, a source region of formed in the major surface portion of the semiconductor substrate structure, a drain region formed in the major surface portion of the semiconductor substrate structure and spaced from the control gate region and the source region, a second gate insulating film provided over that area between the source and drain regions, and a floating gate electrode extending from the first gate insulating film to the second gate insulating film, since the word line extends below the major surface, the word line does not consume a real estate of the semiconductor substrate structure and, accordingly, enhances the integration density of the non-volatile memory device.

摘要翻译： 非易失性存储器件制造在半导体衬底结构上，并且包括由半导体衬底结构中的掩埋层形成的字线和与字线相关联的多个存储单元，并且每个存储器单元包括控制栅极 形成在半导体衬底结构中并从字线延伸到半导体衬底结构的主表面部分的第一栅极绝缘膜，覆盖控制栅极区域的顶表面的第一栅极绝缘膜，形成在主表面部分中的源极区域 形成在所述半导体衬底结构的主表面部分中并与所述控制栅极区域和所述源极区域间隔开的漏极区域，设置在所述源极和漏极区域之间的所述区域上的第二栅极绝缘膜，以及 从第一栅极绝缘膜延伸到第二栅极绝缘膜的浮栅电极 d线延伸到主表面下方，字线不消耗半导体衬底结构的不动产，因此提高了非易失性存储器件的集成密度。

公开(公告)号：US6051466A

公开(公告)日：2000-04-18

申请号：US892199

申请日：1997-07-14

申请人： Shoichi Iwasa

发明人： Shoichi Iwasa

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/8234 ,  H01L21/20 ,  H01L21/22 ,  H01L21/38

CPC分类号： H01L27/10844 ,  H01L27/10808

摘要： The semiconductor memory device comprises a field shield element isolation structure for defining a plurality of element regions electrically isolated from one another; a plurality of memory cells disposed in a matrix of rows and columns, each including a transistor having two impurity diffusion layers, a gate electrode and a capacitor; a plurality of bit lines extending in a row direction; a plurality of word lines extending in a column direction; a plurality of memory cell pairs, each formed in one of the element regions and including adjacent two of the memory cells disposed in the row direction, wherein each of the transistors of the two memory cells in each memory cell pair has two impurity diffusion layers, one of which is common to both the transistors and connected to one of the bit lines extending in the row direction immediately thereabove through a first pad polycrystalline silicon film; a second pad polycrystalline silicon film formed on the other impurity diffusion layer of each transistor so as to extend over a portion of the element isolation structure defining the element region and adjacent thereto in the column direction; and a lower electrode of a capacitor of each memory cell in each memory cell pair formed on and insulated from the bit line connected to the common impurity diffusion layer of the respective transistors and connected to the other impurity diffusion layer of the transistor through one of the second pad polycrystalline films.

摘要翻译： 半导体存储器件包括用于限定彼此电隔离的多个元件区域的场屏蔽元件隔离结构; 设置在行和列的矩阵中的多个存储单元，每个存储单元包括具有两个杂质扩散层的晶体管，栅电极和电容器; 沿行方向延伸的多个位线; 沿列方向延伸的多个字线; 多个存储单元对，分别形成在一个元件区域中，并且包括沿行方向布置的相邻的两个存储单元，其中每个存储单元对中的两个存储单元的晶体管中的每一个具有两个杂质扩散层， 其中之一对于两个晶体管是共同的，并且通过第一焊盘多晶硅膜连接到沿着行方向在其上方延伸的位线之一; 形成在每个晶体管的另一个杂质扩散层上的第二焊盘多晶硅膜，以便在限定元件区域并沿列方向相邻的元件隔离结构的一部分上延伸; 以及每个存储单元对中的每个存储单元的电容器的下电极，形成在与各个晶体管的公共杂质扩散层相连的位线上并与其绝缘，并通过其中的一个连接到晶体管的另一个杂质扩散层 第二垫多晶膜。

公开(公告)号：US5798545A

公开(公告)日：1998-08-25

申请号：US580461

申请日：1995-12-27

申请人： Shoichi Iwasa ,  Tomofune Tani

发明人： Shoichi Iwasa ,  Tomofune Tani

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/10861 ,  H01L27/10832

摘要： A semiconductor substrate has two element forming regions and one element separation region between the two element forming regions. A shield electrode for electrically separating the two element forming regions is formed in the semiconductor substrate at the element separating region. A trench capacitor is formed in the semiconductor substrate at the element separation region. The trench capacitor has a trench, a first conductive layer covering at least the inner wall of the trench, a dielectric layer formed at least on the first conductive layer in the trench, and a second conductive layer formed at least on the dielectric layer in the trench. The shield electrode and the first conductive layer is made of the same layer. A transistor having a pair of impurity doped regions is formed in the semiconductor substrate at the element forming region, the second conductive layer of the trench capacitor is electrically connected to one of the pair of impurity doped regions of the transistor.

摘要翻译： 半导体衬底具有两个元件形成区域和两个元件形成区域之间的一个元件分离区域。 在元件分离区域的半导体衬底中形成用于电分离两个元件形成区域的屏蔽电极。 在元件分离区域的半导体衬底中形成沟槽电容器。 所述沟槽电容器具有沟槽，至少覆盖所述沟槽的内壁的第一导电层，至少形成在所述沟槽中的所述第一导电层上的电介质层，以及至少形成在所述沟槽中的所述电介质层上的第二导电层 沟。 屏蔽电极和第一导电层由相同的层制成。 在元件形成区域的半导体衬底中形成具有一对杂质掺杂区域的晶体管，沟槽电容器的第二导电层电连接到该晶体管的一对杂质掺杂区域中的一个。

公开(公告)号：US5686746A

公开(公告)日：1997-11-11

申请号：US521445

申请日：1995-08-30

申请人： Shoichi Iwasa

发明人： Shoichi Iwasa

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10844 ,  H01L27/10808

摘要： A semiconductor memory device comprises a field shield element isolation structure defining a plurality of electrically isolated element regions and a plurality of memory cells in a matrix of rows and columns, each including a transistor having two impurity diffusion layers, a gate electrode and a capacitor. A plurality of bit lines extends in a row direction and a plurality of word lines in a column direction. A memory cell pair is formed in each of the element regions and includes two adjacent memory cells disposed in the row direction. Each of the transistors of the two memory cells in each pair has two impurity diffusion layers, one of which is common to both transistors and connected to one of the bit lines extending in the row direction immediately thereabove through a first pad polycrystalline silicon film. A second pad is formed on the other impurity diffusion layer of each transistor to extend over a portion of the element isolation structure and adjacent thereto in the column direction. A lower electrode of a capacitor of memory cell in each pair is formed on and insulated from the bit line connected to the common impurity diffusion layer of the respective transistors and to the other impurity diffusion layer through one of the second pad polycrysatalline films.

摘要翻译： 半导体存储器件包括限定多个电隔离元件区域和行和列矩阵中的多个存储单元的场屏蔽元件隔离结构，每个存储单元包括具有两个杂质扩散层的晶体管，栅电极和电容器。 多个位线在行方向上延伸，并且在列方向上延伸多个字线。 在每个元件区域中形成存储单元对，并且包括沿行方向布置的两个相邻的存储单元。 每对中的两个存储单元的每个晶体管具有两个杂质扩散层，其中一个是两个晶体管共同的，并且通过第一焊盘多晶硅膜连接到沿着行方向上延伸的位线之一。 在每个晶体管的另一个杂质扩散层上形成第二焊盘，以沿着列方向延伸到元件隔离结构的一部分上并与其相邻。 每对存储单元的电容器的下电极形成在与各个晶体管的公共杂质扩散层相连的位线上并与其绝缘，并通过第二焊盘多晶硅膜之一与另一个杂质扩散层绝缘。