公开(公告)号：US20070232083A1

公开(公告)日：2007-10-04

申请号：US11727519

申请日：2007-03-27

申请人： Takaharu Itani

发明人： Takaharu Itani

IPC分类号： H01L21/00

CPC分类号： H01L21/67115 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/6659

摘要： An apparatus for manufacturing a semiconductor device includes a treatment chamber in which a working substrate is disposed; a plurality of lamps provided above the treatment chamber; and a reflector provided behind the lamps relative to a direction towards the working substrate, spatially controlling an in-plane distribution of reflection rate of light beams from the lamps, and irradiating the working substrate with light from the lamps.

摘要翻译： 一种用于制造半导体器件的设备，包括：处理室，其中设置有工作基板; 设置在处理室上方的多个灯; 以及设置在灯之后的反射器相对于朝向工作基板的方向的反射器，空间地控制来自灯的光束的反射率的面内分布，以及用来自灯的光照射工作基板。

公开(公告)号：US08148717B2

公开(公告)日：2012-04-03

申请号：US12929504

申请日：2011-01-28

申请人： Takayuki Ito ,  Yusuke Oshiki ,  Kouji Matsuo ,  Kenichi Yoshino ,  Takaharu Itani ,  Takuo Ohashi ,  Toshihiko Iinuma ,  Kiyotaka Miyano ,  Kunihiro Miyazaki

发明人： Takayuki Ito ,  Yusuke Oshiki ,  Kouji Matsuo ,  Kenichi Yoshino ,  Takaharu Itani ,  Takuo Ohashi ,  Toshihiko Iinuma ,  Kiyotaka Miyano ,  Kunihiro Miyazaki

IPC分类号： H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L21/823807 ,  H01L21/2686 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y≦1E-5exp (21541/T).

摘要翻译： 一种半导体装置的制造方法，其特征在于，在半导体基板的由第一原子构成的表面上形成有与半导体基板的表面的面积为5〜30％的开口率y的开口的开口部; 在所述开口中形成外延层，所述外延层由含有15〜25％的浓度的第二原子的混合晶体构成，所述第二原子的晶格常数不同于所述第一原子的晶格常数; 将杂质离子注入到外延层中; 并在预定温度T下进行活化退火，预定温度T等于或高于1150℃，并且满足y＆nlE; 1E-5exp（21541 / T）的关系。

公开(公告)号：US08101974B2

公开(公告)日：2012-01-24

申请号：US12328551

申请日：2008-12-04

申请人： Hiroshi Ohno ,  Takaharu Itani ,  Eiji Morifuji ,  Norikazu Ooishi ,  Toshihiko Iinuma ,  Yoshinori Honguh

发明人： Hiroshi Ohno ,  Takaharu Itani ,  Eiji Morifuji ,  Norikazu Ooishi ,  Toshihiko Iinuma ,  Yoshinori Honguh

IPC分类号： H01L27/10 ,  H01L29/76 ,  H01L29/94 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L21/2686 ,  H01L21/268 ,  H01L21/823437 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device subjected to an optical annealing process by radiation light whose principal wavelength is 1.5 μm or less includes a circuit pattern region formed on a semiconductor substrate, and a dummy pattern region formed separately from the circuit pattern region on the semiconductor substrate. The circuit pattern region has an integrated circuit pattern containing a gate pattern related to a circuit operation. The dummy pattern region has dummy gate patterns that have the same structure as that of a gate pattern used in the integrated circuit pattern and the dummy gate patterns are repeatedly arranged with a pitch 0.4 times or less the principal wavelength.

摘要翻译： 通过主要波长为1.5μm或更小的辐射光进行光学退火处理的半导体器件包括形成在半导体衬底上的电路图案区域和与半导体衬底上的电路图案区域分开形成的虚设图案区域。 电路图案区域具有包含与电路操作相关的栅极图案的集成电路图案。 伪图案区域具有与集成电路图案中使用的栅极图案相同的结构的伪栅极图案，并且虚设栅极图案以主要波长的0.4倍或更小的间距重复排列。

公开(公告)号：US20110127578A1

公开(公告)日：2011-06-02

申请号：US12929504

申请日：2011-01-28

申请人： Takayuki Ito ,  Yusuke Oshiki ,  Kouji Matsuo ,  Kenichi Yoshino ,  Takaharu Itani ,  Takuo Ohashi ,  Toshihiko Iinuma ,  Kiyotaka Miyano ,  Kunihiro Miyazaki

发明人： Takayuki Ito ,  Yusuke Oshiki ,  Kouji Matsuo ,  Kenichi Yoshino ,  Takaharu Itani ,  Takuo Ohashi ,  Toshihiko Iinuma ,  Kiyotaka Miyano ,  Kunihiro Miyazaki

IPC分类号： H01L29/12

CPC分类号： H01L21/823807 ,  H01L21/2686 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y≦1E-5exp (21541/T).

摘要翻译： 一种半导体装置的制造方法，其特征在于，在半导体基板的由第一原子构成的表面上形成有与半导体基板的表面的面积为5〜30％的开口率y的开口的开口部; 在所述开口中形成外延层，所述外延层由含有15〜25％的浓度的第二原子的混合晶体构成，所述第二原子的晶格常数不同于所述第一原子的晶格常数; 将杂质离子注入到外延层中; 并在预定温度T下进行活化退火，预定温度T等于或高于1150℃，并且满足y＆nlE; 1E-5exp（21541 / T）的关系。

公开(公告)号：US20090146310A1

公开(公告)日：2009-06-11

申请号：US12328551

申请日：2008-12-04

申请人： Hiroshi Ohno ,  Takaharu Itani ,  Eiji Morifuji ,  Norikazu Ooishi ,  Toshihiko Iinuma ,  Yoshinori Honguh

发明人： Hiroshi Ohno ,  Takaharu Itani ,  Eiji Morifuji ,  Norikazu Ooishi ,  Toshihiko Iinuma ,  Yoshinori Honguh

IPC分类号： H01L23/48 ,  H01L21/3205

CPC分类号： H01L21/2686 ,  H01L21/268 ,  H01L21/823437 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device subjected to an optical annealing process by radiation light whose principal wavelength is 1.5 μm or less includes a circuit pattern region formed on a semiconductor substrate, and a dummy pattern region formed separately from the circuit pattern region on the semiconductor substrate. The circuit pattern region has an integrated circuit pattern containing a gate pattern related to a circuit operation. The dummy pattern region has dummy gate patterns that have the same structure as that of a gate pattern used in the integrated circuit pattern and the dummy gate patterns are repeatedly arranged with a pitch 0.4 times or less the principal wavelength.

摘要翻译： 通过主要波长为1.5μm或更小的辐射光进行光学退火处理的半导体器件包括形成在半导体衬底上的电路图案区域和与半导体衬底上的电路图案区域分开形成的虚设图案区域。 电路图案区域具有包含与电路操作相关的栅极图案的集成电路图案。 伪图案区域具有与集成电路图案中使用的栅极图案相同的结构的伪栅极图案，并且虚设栅极图案以主要波长的0.4倍或更小的间距重复排列。

公开(公告)号：US20090137107A1

公开(公告)日：2009-05-28

申请号：US12323977

申请日：2008-11-26

申请人： Takaharu Itani

发明人： Takaharu Itani

IPC分类号： H01L21/283

CPC分类号： H01L21/28518 ,  H01L21/268 ,  H01L21/28052 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475

摘要： A method of manufacturing a semiconductor device according to an embodiment of the invention includes forming patterns on a substrate, depositing a light absorption layer on the patterns, processing the light absorption layer to form a first region which includes a first type of pattern included in the patterns and is coated with the light absorption layer having a first thickness, a second region which includes a second type of pattern included in the patterns and is coated with the light absorption layer having a second thickness thinner than the first thickness, and a third region which includes a third type of pattern included in the patterns and is coated with the light absorption layer having a third thickness thinner than the second thickness, and annealing the substrate by radiating light on the substrate.

摘要翻译： 根据本发明的实施例的制造半导体器件的方法包括在衬底上形成图案，在图案上沉积光吸收层，处理光吸收层以形成第一区域，该第一区域包括第一类型 并且涂覆有具有第一厚度的光吸收层，第二区域，其包括包含在图案中的第二类型图案，并且涂覆有具有比第一厚度薄的第二厚度的光吸收层，以及第三区域 其包括图案中包括的第三类型图案，并且涂覆有具有比第二厚度薄的第三厚度的光吸收层，并且通过在基板上照射光使基板退火。

公开(公告)号：US07084068B2

公开(公告)日：2006-08-01

申请号：US10661564

申请日：2003-09-15

申请人： Kyoichi Suguro ,  Takayuki Ito ,  Takaharu Itani

发明人： Kyoichi Suguro ,  Takayuki Ito ,  Takaharu Itani

IPC分类号： H01L21/302 ,  H01L21/461 ,  C23C16/00

CPC分类号： H01L21/28185 ,  H01L21/02046 ,  H01L21/02233 ,  H01L21/02247 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/28238 ,  H01L21/3144 ,  H01L21/32 ,  H01L21/67115 ,  H01L21/67155 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518

摘要： An annealing furnace, includes a processing chamber configured to store a substrate; a susceptor located in the processing chamber so as to load the substrate and having an auxiliary heater for heating the substrate at 650° C. or less, the susceptor having a surface being made of quartz; a gas supply system configured to supply a gas required for a thermal processing on the substrate in parallel to a surface of the substrate; a transparent window located on an upper part of the processing chamber facing the susceptor; and a main heater configured to irradiate a pulsed light on the surface of the substrate to heat the substrate from the transparent window, the pulsed light having a pulse duration of approximately 0.1 ms to 200 ms and having a plurality of emission wavelengths.

摘要翻译： 一种退火炉，包括：配置成存储基板的处理室; 位于所述处理室中的基座，以便加载所述基板并具有用于在650℃以下加热所述基板的辅助加热器，所述基座具有由石英制成的表面; 气体供给系统，被配置为平行于所述基板的表面在所述基板上供给热处理所需的气体; 位于处理室的与感受器相对的上部的透明窗口; 以及主加热器，其被配置为在所述基板的表面上照射脉冲光以从所述透明窗加热所述基板，所述脉冲光具有约0.1ms至200ms的脉冲持续时间并且具有多个发射波长。

公开(公告)号：US5246789A

公开(公告)日：1993-09-21

申请号：US822673

申请日：1992-01-21

申请人： Takaharu Itani ,  Masaru Nikaido ,  Hideki Yamaguchi

发明人： Takaharu Itani ,  Masaru Nikaido ,  Hideki Yamaguchi

IPC分类号： G09F9/33 ,  H05B33/04 ,  H05B33/10 ,  H05B33/26

CPC分类号： G09F9/33 ,  H05B33/04 ,  H05B33/10 ,  H05B33/26

摘要： An AC powder type EL panel includes an AC powder type EL element, thermoplastic adhesive layers formed on all surfaces of the AC powder type EL element, and a pair of protective films adhered to cover substantially the entire surfaces of the thermoplastic adhesive layers and having end portions to be fused to each other to seal the AC powder type EL element. A thickness ratio of the protective film to the thermoplastic adhesive layer is within the range of 5:1 to 2:1. Since the thermocompression-bonded end portions of the thermoplastic adhesive layers having poor moisture barrier properties are not exposed between the protective films at the end portions of the AC powder type EL panel, penetration of external moisture into the panel can be effectively prevented.

摘要翻译： 交流粉末型EL面板包括AC粉末型EL元件，在AC粉末型EL元件的所有表面上形成的热塑性粘合剂层，以及一对保护膜，其粘附到基本上覆盖热塑性粘合剂层的整个表面并具有末端 彼此熔合的部分以密封AC粉末型EL元件。 保护膜与热塑性粘合剂层的厚度比在5:1〜2:1的范围内。 由于在AC粉末型EL面板的端部的保护膜之间没有露出具有差的防潮性的热塑性粘合剂层的热压粘合端部，因此可以有效地防止外部水分渗透到面板中。

公开(公告)号：US07902030B2

公开(公告)日：2011-03-08

申请号：US12483728

申请日：2009-06-12

申请人： Takayuki Ito ,  Yusuke Oshiki ,  Kouji Matsuo ,  Kenichi Yoshino ,  Takaharu Itani ,  Takuo Ohashi ,  Toshihiko Iinuma ,  Kiyotaka Miyano ,  Kunihiro Miyazaki

发明人： Takayuki Ito ,  Yusuke Oshiki ,  Kouji Matsuo ,  Kenichi Yoshino ,  Takaharu Itani ,  Takuo Ohashi ,  Toshihiko Iinuma ,  Kiyotaka Miyano ,  Kunihiro Miyazaki

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/2686 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y≦1E-5exp(21541/T).

摘要翻译： 一种半导体装置的制造方法，其特征在于，在半导体基板的由第一原子构成的表面上形成有与半导体基板的表面的面积为5〜30％的开口率y的开口的开口部; 在所述开口中形成外延层，所述外延层由含有15〜25％的浓度的第二原子的混合晶体构成，所述第二原子的晶格常数不同于所述第一原子的晶格常数; 将杂质离子注入到外延层中; 并在预定温度T下进行活化退火，预定温度T等于或高于1150℃，并且满足y＆nlE; 1E-5exp（21541 / T）的关系。

公开(公告)号：US07279405B2

公开(公告)日：2007-10-09

申请号：US10980232

申请日：2004-11-04

申请人： Takaharu Itani ,  Takayuki Ito ,  Kyoichi Suguro

发明人： Takaharu Itani ,  Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/425

CPC分类号： H01L21/26533 ,  H01L21/324 ,  H01L29/6659

摘要： A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion maybe controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.

摘要翻译： 通过退火形成具有注入离子的高激活速率，低电阻率和受控的漏电流的浅p-n结扩散层。 通过光照射进行杂质掺杂后的退火。 这些杂质通过在将杂质掺杂到半导体衬底11之后通过光照射退火至少两次来激活。光辐射的特征在于使用W卤素灯RTA或闪光灯FLA，除了使用闪光灯FLA的最终光照射 。 杂质扩散可以被控制到最小，并且当在MOSFET的源极和漏极延伸区域中形成离子注入层时，在杂质掺杂过程中已经发展出的晶体缺陷可以被充分地减小，或者源中的离子注入层和 漏区。