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    Manufacturing method for semiconductor device
    1.
    发明授权
    Manufacturing method for semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US08759182B2

    公开(公告)日：2014-06-24

    申请号：US13459740

    申请日：2012-04-30

    Applicant: Hyun-Jun Sim ,  Jae-Young Park ,  Hyun-Seung Kim ,  Sang-Bom Kang ,  Sun-Ghil Lee ,  Hyun-Deok Yang ,  Kang-Hun Moon ,  Han-Ki Lee ,  Sang-Mi Choi

    Inventor： Hyun-Jun Sim ,  Jae-Young Park ,  Hyun-Seung Kim ,  Sang-Bom Kang ,  Sun-Ghil Lee ,  Hyun-Deok Yang ,  Kang-Hun Moon ,  Han-Ki Lee ,  Sang-Mi Choi

    IPC: H01L21/336

    CPC classification number: H01L29/6659 ,  H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

    Abstract: A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal.

    Abstract translation: 通过在基板上形成第一绝缘层，在第一绝缘层上进行第一次氮化，形成第二绝缘层，依次进行第一和第二退火，制造具有改善的负偏压温度不稳定寿命特性的半导体器件 第二绝缘层以形成第三绝缘层，其中所述第二退火在比所述第一退火更高的温度和不同的气体下进行。 在第三绝缘层上进行第二次氮化，以形成第四绝缘层，并且在第四绝缘层上顺序的第三和第四退火形成第五绝缘层。 第三退火在比第一退火更高的温度下进行，第四退火在比第二退火更高的温度下进行，并且具有比第三退火不同的气体。

    Semiconductor device and method of fabricating the same
    2.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08470703B2

    公开(公告)日：2013-06-25

    申请号：US13105195

    申请日：2011-05-11

    Applicant: Byung-Hak Lee ,  Yu-Gyun Shin ,  Sang-Woo Lee ,  Sun-Ghil Lee ,  Jin-Bum Kim ,  Joon-Gon Lee

    Inventor： Byung-Hak Lee ,  Yu-Gyun Shin ,  Sang-Woo Lee ,  Sun-Ghil Lee ,  Jin-Bum Kim ,  Joon-Gon Lee

    IPC: H01L21/3205

    CPC classification number: H01L21/28518 ,  H01L21/823807 ,  H01L21/823814

    Abstract: Methods of forming a semiconductor device include providing a substrate having an area including a source and a drain region of a transistor. A nickel (Ni) metal film is formed on the substrate area including the source and the drain region. A first heat-treatment process is performed including heating the substrate including the metal film from a first temperature to a second temperature at a first ramping rate and holding the substrate including the metal film at the second temperature for a first period of time. A second heat-treatment process is then performed including heating the substrate including the metal film from a third temperature to a fourth temperature at a second ramping rate and holding the substrate at the fourth temperature for a second period of time. The fourth temperature is different from the second temperature and the second period of time is different from the first period of time. The sequentially performed first and second heat-treatment processes convert the Ni metal layer on the source and drain regions into a NiSi layer on the source and drain regions and a NiSi2 layer between the NiSi layer and the source and drain regions.

    Abstract translation: 形成半导体器件的方法包括提供具有包括晶体管的源极和漏极区域的区域的衬底。 在包括源极和漏极区域的衬底区域上形成镍（Ni）金属膜。 执行第一热处理工艺，包括以第一斜率从第一温度至第二温度加热包括金属膜的基板，并将包含金属膜的基板在第二温度下保持第一时间段。 然后执行第二热处理工艺，包括以第二斜率从第三温度至第四温度加热包括金属膜的衬底，并将衬底保持在第四温度第二时间段。 第四温度与第二温度不同，第二时间段与第一时间段不同。 依次执行的第一和第二热处理工艺将源极和漏极区域上的Ni金属层转换成源极和漏极区域上的NiSi层以及NiSi层与源极和漏极区域之间的NiSi 2层。

    Method of manufacturing semiconductor device having stress creating layer
    3.
    发明授权
    Method of manufacturing semiconductor device having stress creating layer 有权
    具有应力产生层的半导体器件的制造方法

    公开(公告)号：US08409947B2

    公开(公告)日：2013-04-02

    申请号：US12693080

    申请日：2010-01-25

    Applicant: Jin-bum Kim ,  Wook-je Kim ,  Yu-gyun Shin ,  Kwan-heum Lee ,  Sun-ghil Lee

    Inventor： Jin-bum Kim ,  Wook-je Kim ,  Yu-gyun Shin ,  Kwan-heum Lee ,  Sun-ghil Lee

    IPC: H01L21/8238

    CPC classification number: H01L29/7848 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

    Abstract: Provided is a simplified method of manufacturing a semiconductor device having a stress creating layer. A first conductive first impurity region is formed on a semiconductor substrate on both sides of a first gate of a first area of the semiconductor substrate, and a second conductive second impurity region is formed on the semiconductor substrate on both sides of a second gate of a second area. First and second spacers are formed on sidewalls of the first and second gates, respectively. First and second semiconductor layers are formed in portions of the semiconductor substrate so as to contact the first and second impurity regions, respectively. The second semiconductor layer is removed. First and second barrier layers are formed in the first and second contact holes of the insulation layer, respectively.

    Abstract translation: 提供了一种制造具有应力产生层的半导体器件的简化方法。 在半导体衬底的第一区域的第一栅极的两侧上的半导体衬底上形成第一导电第一杂质区，并且在半导体衬底的第二栅极的两侧的半导体衬底上形成第二导电第二杂质区 第二区。 第一和第二间隔物分别形成在第一和第二栅极的侧壁上。 第一半导体层和第二半导体层分别形成在半导体衬底的部分中，以分别接触第一和第二杂质区。 去除第二半导体层。 第一和第二阻挡层分别形成在绝缘层的第一和第二接触孔中。

    Method of manufacturing semiconductor device
    4.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08361860B2

    公开(公告)日：2013-01-29

    申请号：US12656130

    申请日：2010-01-19

    Applicant: Jin-bum Kim ,  Wook-je Kim ,  Kwan-heum Lee ,  Yu-gyun Shin ,  Sun-ghil Lee

    Inventor： Jin-bum Kim ,  Wook-je Kim ,  Kwan-heum Lee ,  Yu-gyun Shin ,  Sun-ghil Lee

    IPC: H01L21/8242

    CPC classification number: H01L21/7687 ,  H01L27/10855 ,  H01L28/91

    Abstract: A method of manufacturing a semiconductor device may include forming a first interlayer insulation layer on a substrate including at least one gate structure formed thereon, the substrate having a plurality of source/drain regions formed on both sides of the at least one gate structure, forming at least one buried contact plug on at least one of the plurality of source/drain regions and in the first interlayer insulation layer, forming a second interlayer insulation layer on the first interlayer insulation layer and the at least one buried contact plug, exposing the at least one buried contact plug in the second interlayer insulation layer by forming at least one contact hole, implanting ions in the at least one contact hole in order to create an amorphous upper portion of the at least one buried contact plug, depositing a lower electrode layer on the second interlayer insulation layer and the at least one contact hole, and forming a metal silicide layer in the amorphous upper portion of the at least one buried contact plug.

    Abstract translation: 制造半导体器件的方法可以包括在包括形成在其上的至少一个栅极结构的衬底上形成第一层间绝缘层，所述衬底具有形成在所述至少一个栅极结构的两侧上的多个源/漏区，形成 在所述多个源极/漏极区域和所述第一层间绝缘层中的至少一个上的至少一个埋置的接触插塞，在所述第一层间绝缘层和所述至少一个埋置的接触插塞上形成第二层间绝缘层， 通过形成至少一个接触孔，在所述至少一个接触孔中注入离子，以形成所述至少一个埋入接触插塞的非晶体上部，沉积下部电极层 在所述第二层间绝缘层和所述至少一个接触孔上，并且在所述非晶体上部形成金属硅化物层 的所述至少一个埋入式接触插塞。

    NAND-type flash memory devices including selection transistors with an anti-punchthrough impurity region and methods of fabricating the same
    7.
    发明授权
    NAND-type flash memory devices including selection transistors with an anti-punchthrough impurity region and methods of fabricating the same 有权
    包括具有抗穿透杂质区域的选择晶体管的NAND型闪存器件及其制造方法

    公开(公告)号：US07683421B2

    公开(公告)日：2010-03-23

    申请号：US11849533

    申请日：2007-09-04

    Applicant: Gyoung-Ho Buh ,  Sun-Ghil Lee ,  Jong-Ryeol Yoo ,  Deok-Hyung Lee ,  Guk-Hyon Yon

    Inventor： Gyoung-Ho Buh ,  Sun-Ghil Lee ,  Jong-Ryeol Yoo ,  Deok-Hyung Lee ,  Guk-Hyon Yon

    IPC: H01L29/10

    CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/12 ,  H01L29/1083 ,  H01L29/78

    Abstract: A NAND-type flash memory device including selection transistors is provided. The device includes first and second impurity regions formed in a semiconductor substrate, and first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions. The first and second selection gate patterns are disposed adjacent to the first and second impurity regions, respectively. A plurality of cell gate patterns are disposed between the first and second selection gate patterns. A first anti-punchthrough impurity region that surrounds the first impurity region is provided in the semiconductor substrate. The first anti-punchthrough impurity region overlaps with a first edge of the first selection gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region that surrounds the second impurity region is provided in the semiconductor substrate. The second anti-punchthrough impurity region overlaps with a first edge of the second selection gate pattern adjacent to the second impurity region.

    Abstract translation: 提供了包括选择晶体管的NAND型闪速存储器件。 该器件包括形成在半导体衬底中的第一和第二杂质区，以及设置在第一和第二杂质区之间的半导体衬底上的第一和第二选择栅极图案。 第一和第二选择栅极图案分别与第一和第二杂质区相邻设置。 多个单元栅极图案设置在第一和第二选择栅极图案之间。 在半导体衬底中设置围绕第一杂质区的第一抗穿透杂质区。 第一抗穿透杂质区域与第一选择栅极图案的与第一杂质区域相邻的第一边缘重叠。 在半导体衬底中设置有围绕第二杂质区的第二抗穿透杂质区。 第二抗穿透杂质区域与第二选择栅极图案的与第二杂质区域相邻的第一边缘重叠。

    Fin field effect transistors having multi-layer fin patterns and methods of forming the same
    9.
    发明申请
    Fin field effect transistors having multi-layer fin patterns and methods of forming the same 失效
    具有多层翅片图案的鳍式场效应晶体管及其形成方法

    公开(公告)号：US20050184316A1

    公开(公告)日：2005-08-25

    申请号：US10870743

    申请日：2004-06-17

    Applicant: Young-Pil Kim ,  Sun-Ghil Lee ,  Si-Young Choi

    Inventor： Young-Pil Kim ,  Sun-Ghil Lee ,  Si-Young Choi

    IPC: H01L21/336 ,  H01L29/745 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

    CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/78687

    Abstract: A fin field effect transistor has a fin pattern protruding from a semiconductor substrate. The fin pattern includes first semiconductor patterns and second semiconductor patterns which are stacked. The first and second semiconductor patterns have lattice widths that are greater than a lattice width of the substrate in at least one direction. In addition, the first and second semiconductor patterns may be alternately stacked to increase the height of the fin pattern, such that one of the first and second patterns can reduce stress from the other of the first and second patterns. The first and second semiconductor patterns may be formed of strained silicon and silicon-germanium, where the silicon-germanium patterns can reduce stress from the strained silicon patterns. Therefore, both the number of carriers and the mobility of carriers in the transistor channel may be increased, improving performance of the fin field effect transistor. Related methods are also discussed.

    Abstract translation: 鳍状场效应晶体管具有从半导体衬底突出的鳍状图案。 鳍状图案包括堆叠的第一半导体图案和第二半导体图案。 第一和第二半导体图案具有在至少一个方向上大于衬底的晶格宽度的晶格宽度。 此外，第一和第二半导体图案可以交替堆叠以增加鳍片图案的高度，使得第一和第二图案中的一个可以减小来自第一和第二图案中的另一个的应力。 第一和第二半导体图案可以由应变硅和硅 - 锗形成，其中硅 - 锗图案可以减小应变硅图案的应力。 因此，可以增加晶体管沟道中的载流子数和载流子的迁移率，从而提高鳍式场效应晶体管的性能。 还讨论了相关方法。

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