摘要:
According to one embodiment, a pattern forming system includes a patterning tool, a multi-axis robot, and a simulation tool that are coupled to a pattern forming tool that is executed on a suitable computing system. The pattern forming tool receives a contour measurement from the patterning tool and transmits the measured contour to the simulation tool to model the electrical characteristics of a conductive pattern or a dielectric pattern on the measured contour. Upon receipt of the modeled characteristics, the pattern forming system may adjust one or more dimensions of the pattern according to the model, and subsequently create, using the patterning tool, the corrected pattern on the surface.
摘要:
A method of forming an electrically conductive via with bumps on both sides of a substrate wherein there is provided a substrate having a pair of opposing surfaces and a via extending between the opposing surfaces. A layer of a material capable of forming a seed for receiving thereon a plating material is provided on one of the surfaces extending to the via. The structure is then placed into an electroplating bath, preferably gold-containing, to electroplate the walls of the via. The electroplated material is then heated to a temperature above its flow or melting temperature in a reducing atmosphere for a time sufficient to cause the electroplated material to fill the via and any voids within the via. The step of heating the electroplated material is preferably to a temperature at least 10 degrees C. above its flow or melting temperature of the electroplated material. The reducing atmosphere is from about 5 percent to 100 percent hydrogen and the remainder preferably nitrogen. The step of electroplating can include electroplating of sufficient electroplated material in the via to provide a bump on at least one of the surfaces heating.
摘要:
A novel capillary die and crystal growing method are provided for growing a hollow crystalline body by EFG. Inner and outer annular moats surround the die tip. Passageways are provided for supplying melt to those moats from a crucible, so that melt in said moats will wet and cover the inner and outer exterior surfaces of the die tip during growth of a hollow crystalline body. The novel die may be constructed so as to have a lower die tip and a shorter capillary than EFG dies heretofore used to successfully grow hollow bodies. The die design facilitates keeping the temperature of the die tip substantially uniform about its circumference, thereby improving the uniformity of thickness of the wall of the crystalline body grown from a film of melt on the die tip. The moats reduce the likelihood of the growth process being interrupted or adversely affected by flooding of the die. In the event the growth meniscus breaks, liquid silicon is captured in the moats, thereby preventing or reducing the likelihood of flooding of the die and associated growth apparatus.
摘要:
An method for building multi-layer circuits without post process via fills is disclosed. The method includes aligning a first contact on a first substrate layer with a second contact on a second substrate layer; and fusion bonding the first contact to the second contact. A multilayer circuit is also disclosed. The multilayer circuit includes a first substrate layer including a first contact. The multilayer circuit also includes a second substrate layer including a second contact that is fusion bonded to the first contact such that the first and second contacts are aligned.
摘要:
A novel capillary die and crystal growing method are provided for growing a hollow crystalline body by EFG. Inner and outer annular moats surround the die tip. Passageways are provided for supplying melt to those moats from a crucible, so that melt in said moats will wet and cover the inner and outer exterior surfaces of the die tip during growth of a hollow crystalline body. The novel die may be constructed so as to have a lower die tip and a shorter capillary than EFG dies heretofore used to successfully grow hollow bodies. The die design facilitates keeping the temperature of the die tip substantially uniform about its circumference, thereby improving the uniformity of thickness of the wall of the crystalline body grown from a film of melt on the die tip. The moats reduce the likelihood of the growth process being interrupted or adversely affected by flooding of the die. In the event the growth meniscus breaks, liquid silicon is captured in the moats, thereby preventing or reducing the likelihood of flooding of the die and associated growth apparatus.
摘要:
Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads.
摘要:
According to one embodiment, a pattern forming system includes a patterning tool, a multi-axis robot, and a simulation tool that are coupled to a pattern forming tool that is executed on a suitable computing system. The pattern forming tool receives a contour measurement from the patterning tool and transmits the measured contour to the simulation tool to model the electrical characteristics of a conductive pattern or a dielectric pattern on the measured contour. Upon receipt of the modeled characteristics, the pattern forming system may adjust one or more dimensions of the pattern according to the model, and subsequently create, using the patterning tool, the corrected pattern on the surface.
摘要:
According to one embodiment of the invention, a method for sealing one or more vias comprises providing a first substrate having vias, forming an adhesion layer on an inner surface of the vias, sandwiching a solder layer between the first substrate and a second substrate, and elevating of the first substrate, second substrate, and solder layer to a temperature above a eutectic point and below a melting point of the solder layer. The act of elevating the solder layer to a temperature above the eutectic point and below the melting point causes the solder layer to flow into the vias in a generally consistent manner.