公开(公告)号：US20200091274A1

公开(公告)日：2020-03-19

申请号：US16134876

申请日：2018-09-18

Applicant: Abhishek SHARMA ,  Ravi PILLARISETTY ,  Brian DOYLE ,  Elijah KARPOV ,  Prashant MAJHI ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI

Inventor： Abhishek SHARMA ,  Ravi PILLARISETTY ,  Brian DOYLE ,  Elijah KARPOV ,  Prashant MAJHI ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI

IPC: H01L49/02 ,  H01L29/51 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a gate dielectric layer adjacent to the channel layer, and a gate electrode separated from the channel layer by the gate dielectric layer. The gate dielectric layer includes a non-linear gate dielectric material. The gate electrode, the channel layer, and the gate dielectric layer form a non-linear capacitor. Other embodiments may be described and/or claimed.

公开(公告)号：US10516109B2

公开(公告)日：2019-12-24

申请号：US15529907

申请日：2014-12-24

Applicant: Niloy Mukherjee ,  Ravi Pillarisetty ,  Prashant Majhi ,  Uday Shah ,  Ryan E Arch ,  Markus Kuhn ,  Justin S. Brockman ,  Huiying Liu ,  Elijah V Karpov ,  Kaan Oguz ,  Brian S. Doyle ,  Robert S. Chau

Inventor： Niloy Mukherjee ,  Ravi Pillarisetty ,  Prashant Majhi ,  Uday Shah ,  Ryan E Arch ,  Markus Kuhn ,  Justin S. Brockman ,  Huiying Liu ,  Elijah V Karpov ,  Kaan Oguz ,  Brian S. Doyle ,  Robert S. Chau

IPC: H01L45/00

Abstract: Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.

公开(公告)号：US10355205B2

公开(公告)日：2019-07-16

申请号：US15528674

申请日：2014-12-18

Applicant: Prashant Majhi ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Uday Shah ,  Elijah V. Karpov ,  Brian S. Doyle ,  Robert S. Chau

Inventor： Prashant Majhi ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Uday Shah ,  Elijah V. Karpov ,  Brian S. Doyle ,  Robert S. Chau

IPC: H01L29/08 ,  H01L45/00

Abstract: Resistive memory cells are described. In some embodiments, the resistive memory cells include a switching layer having an inner region in which one or more filaments is formed. In some instances, the filaments is/are formed only within the inner region of the switching layer. Methods of making such resistive memory cells and devices including such cells are also described.

公开(公告)号：US09443936B2

公开(公告)日：2016-09-13

申请号：US13870184

申请日：2013-04-25

Applicant: Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

Inventor： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC: H01L29/15 ,  H01L21/285 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78 ,  H01L29/80 ,  H01L29/165 ,  H01L29/51

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract translation: 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：US20150123171A1

公开(公告)日：2015-05-07

申请号：US14597128

申请日：2015-01-14

Applicant: MARKO RADOSAVLJEVIC ,  PRASHANT MAJHI ,  JACK T. KAVALIEROS ,  NITI GOEL ,  WILMAN TSAI ,  NILOY MUKHERJEE ,  YONG JU LEE ,  GILBERT DEWEY ,  WILLY RACHMADY

Inventor： MARKO RADOSAVLJEVIC ,  PRASHANT MAJHI ,  JACK T. KAVALIEROS ,  NITI GOEL ,  WILMAN TSAI ,  NILOY MUKHERJEE ,  YONG JU LEE ,  GILBERT DEWEY ,  WILLY RACHMADY

IPC: H01L29/778 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L21/2256 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/47 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

Abstract: Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.

Abstract translation: 描述了III-V半导体器件的电导率改进。 第一改进包括与通道层不共同平面的阻挡层。 第二个改进包括金属/ Si，Ge或硅锗/ III-V堆叠的退火，以在Si和/或锗掺杂的III-V层上形成金属硅，金属锗或金属硅锗层。 然后，去除金属层并在金属硅，金属锗或金属硅锗层上形成源/漏电极。 第三个改进包括在III-V沟道层上形成IV族和/或VI族元素的层，以及退火以使IV族和/或VI族物质掺杂III-V通道层。 第四个改进包括在III-V器件的接近区域上形成的钝化层和/或偶极层。

公开(公告)号：US08921830B2

公开(公告)日：2014-12-30

申请号：US13461962

申请日：2012-05-02

Applicant: Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7842 ,  H01L29/785

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种具有衬底，形成在衬底上的掩埋氧化物层，形成在掩埋氧化物层上的绝缘体上硅（SOI）芯体，围绕着该衬底的压应变量子阱（QW）层） SOI芯，以及围绕QW层缠绕的拉伸应变硅层。 描述和要求保护其他实施例。

公开(公告)号：US08643079B2

公开(公告)日：2014-02-04

申请号：US12115192

申请日：2008-05-05

Applicant: Prashant Majhi ,  Kyu S. Min ,  Wilman Tsai

Inventor： Prashant Majhi ,  Kyu S. Min ,  Wilman Tsai

IPC: H01L29/788

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/0262 ,  H01L21/3141 ,  H01L29/42324

Abstract: Nanocrystal structures formed using atomic layer deposition (ALD) processes are useful in the formation of integrated circuits such as memory devices. Rather than continuing the ALD process until a continuous layer is formed, the ALD process is halted prematurely to leave a discontinuous formation of nanocrystals which are then capped by a different material, thus forming a layer with a discontinuous portion and a bulk portion. Such nanocrystals can serve as charge-storage sites within the bulk portion, and the resulting structure can serve as a floating gate of a floating-gate memory cell. A floating gate may contain one or more layers of such nanocrystal structures.

Abstract translation: 使用原子层沉积（ALD）工艺形成的纳米晶体结构在形成诸如存储器件的集成电路中是有用的。 不是继续ALD过程直到形成连续层，所以ALD过程被过早地停止以留下不连续的纳米晶体形成，然后被不同的材料覆盖，从而形成具有不连续部分和主体部分的层。 这种纳米晶体可以用作体积部分内的电荷存储位置，并且所得结构可以用作浮栅存储器单元的浮置栅极。 浮动栅极可以包含一层或多层这样的纳米晶体结构。

公开(公告)号：US08258498B2

公开(公告)日：2012-09-04

申请号：US13017862

申请日：2011-01-31

Applicant: Prashant Majhi ,  Mantu Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

Inventor： Prashant Majhi ,  Mantu Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC: H01L29/06 ,  H01L31/072 ,  H01L31/0336 ,  H01L31/0328 ,  H01L31/109

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract translation: 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：US20110147798A1

公开(公告)日：2011-06-23

申请号：US12646711

申请日：2009-12-23

Applicant: Marko Radosavljevic ,  Prashant Majhi ,  Jack T. Kavalieros ,  Niti Goel ,  Wilman Tsai ,  Niloy Mukherjee ,  Yong Ju Lee ,  Gilbert Dewey ,  Willy Rachmady

Inventor： Marko Radosavljevic ,  Prashant Majhi ,  Jack T. Kavalieros ,  Niti Goel ,  Wilman Tsai ,  Niloy Mukherjee ,  Yong Ju Lee ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/7786 ,  H01L21/2256 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/47 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

Abstract: Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.

Abstract translation: 描述了III-V半导体器件的电导率改进。 第一改进包括与通道层不共同平面的阻挡层。 第二个改进包括金属/ Si，Ge或硅锗/ III-V堆叠的退火，以在Si和/或锗掺杂的III-V层上形成金属硅，金属锗或金属硅锗层。 然后，去除金属层并在金属硅，金属锗或金属硅锗层上形成源/漏电极。 第三个改进包括在III-V沟道层上形成IV族和/或VI族元素的层，以及退火以使IV族和/或VI族物质掺杂III-V通道层。 第四个改进包括在III-V器件的接近区域上形成的钝化层和/或偶极层。

公开(公告)号：US20100163848A1

公开(公告)日：2010-07-01

申请号：US12347883

申请日：2008-12-31

Applicant: Prashant Majhi ,  Jack Kavalieros ,  Wilman Tsai

Inventor： Prashant Majhi ,  Jack Kavalieros ,  Wilman Tsai

IPC: H01L29/66 ,  H01L29/165 ,  H01L21/20

CPC classification number: H01L29/7782 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02505 ,  H01L21/02532 ,  H01L29/1075

Abstract: Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers.

Abstract translation: 本发明的实施例描述了具有缓冲结构的半导体器件和制造缓冲结构的方法。 缓冲结构形成在衬底和量子阱层之间，以防止由于晶格失配而引起的衬底和量子阱层中的缺陷。 缓冲结构包括形成在基板上的第一缓冲层，形成在第一缓冲层上的多个阻挡构件和形成在多个阻挡构件上的第二缓冲器。 多个阻挡构件防止第二缓冲层直接沉积在整个第一缓冲层上，以便最小化晶格失配并防止第一和第二缓冲层中的缺陷。