公开(公告)号：US09045811B2

公开(公告)日：2015-06-02

申请号：US13482421

申请日：2012-05-29

申请人： Masaki Sano ,  Yoshifumi Abe ,  Kazuhiro Hatano ,  Koji Katsukawa

发明人： Masaki Sano ,  Yoshifumi Abe ,  Kazuhiro Hatano ,  Koji Katsukawa

IPC分类号： C22B11/00 ,  C22B3/04 ,  C22B3/00 ,  C22B3/12 ,  B03D1/02

CPC分类号： C22B11/042 ,  B03D1/02 ,  C22B3/12 ,  C22B11/04 ,  Y02P10/214

摘要： A process of leaching gold can be inexpensively and efficiently carried out from a mixture containing sulfur and gold, typically from the material containing sulfur and gold that is an intermediate product recovered by the flotation method in the hydrometallurgical method. Specifically, the mixture containing elemental sulfur and gold and an aqueous solution of hydroxide of one or more of metals of alkali metals and alkaline earth metals are combined, the hydroxides reacting with elemental sulfur to form thiosulfate of alkali and/or alkaline earth metal, and the gold thereby being leached by reaction with the thiosulfate.

摘要翻译： 浸出金的方法可以从包含硫和金的混合物中经常地和有效地进行，通常来自含有硫和金的材料，其是通过浮选法通过浮选法回收的中间产物。 具体地说，将含有元素硫和金的混合物和一种或多种碱金属和碱土金属的金属的氢氧化物水溶液合并，氢氧化物与元素硫反应形成碱金属和/或碱土金属的硫代硫酸盐，以及 因此通过与硫代硫酸盐反应而浸出金。

公开(公告)号：US20120229179A1

公开(公告)日：2012-09-13

申请号：US13474182

申请日：2012-05-17

申请人： Masaki SANO

发明人： Masaki SANO

IPC分类号： H03L7/08 ,  H03K21/00

CPC分类号： H03L7/08 ,  H03L7/0991 ,  H03L7/16

摘要： A PLL circuit includes a polyphase reference clock output circuit that outputs reference clocks, a polyphase frequency divider circuit that outputs divided clocks, which is obtained by dividing frequencies of the reference clocks, a selection switch circuit that selects one of the reference clocks or one of the divided clocks, and outputs the selected clock as a selected clock, a digital VCO that uses the selected clock as an operating clock, and outputs delay amount data indicating a phase difference between an output clock and an ideal phase, where the output clock has a frequency that fluctuates according to a value of frequency control input data, and the ideal phase is calculated according to the output clock and the value of the frequency control input data, and a selection circuit that selects and outputs the output clock synchronized with the divided clocks according to the delay amount data.

摘要翻译： PLL电路包括输出参考时钟的多相基准时钟输出电路，输出分频时钟的多相分频电路，该分相时钟是通过对基准时钟的频率进行分频而获得的选择开关电路，选择开关电路选择参考时钟之一或者 分频时钟，并将所选择的时钟作为选择的时钟输出，使用所选择的时钟作为工作时钟的数字VCO，并输出指示输出时钟与理想相位之间的相位差的延迟量数据，其中输出时钟具有 根据频率控制输入数据的值而波动的频率，并且根据输出时钟和频率控制输入数据的值来计算理想相位;以及选择电路，其选择并输出与分频的同步的输出时钟 时钟根据延迟量数据。

公开(公告)号：US07680235B2

公开(公告)日：2010-03-16

申请号：US11020133

申请日：2004-12-27

申请人： Masaki Sano ,  Kinji Kayanuma

发明人： Masaki Sano ,  Kinji Kayanuma

IPC分类号： H03D3/24

CPC分类号： H03L7/087 ,  H03D13/003

摘要： A PLL circuit includes a phase comparing section, a low pass filter, a digital VCO circuit, and a frequency divider. The phase comparing section compares an inputted clock signal and a frequency-divided clock signal in phase to detect a phase difference. The low pass filter averages the phase difference outputted from the phase comparing section to output the averaged result as a frequency control input. The digital VCO circuit operates in synchronism with a reference clock signal, and generates a sync clock signal based on the frequency control input while a phase of the sync clock signal is controlled in units of predetermined resolution values. The predetermined resolution value is a 1/K (K is a natural number more than 1) of a period of the reference clock signal. The frequency divider frequency-divides the synch clock signal to generate the frequency-divided clock signal.

摘要翻译： PLL电路包括相位比较部分，低通滤波器，数字VCO电路和分频器。 相位比较部分将输入的时钟信号和分频时钟信号同相进行比较，以检测相位差。 低通滤波器对从相位比较部分输出的相位差进行平均，以将平均结果输出为频率控制输入。 数字VCO电路与参考时钟信号同步工作，并且在以预定分辨率值为单位控制同步时钟信号的相位时，基于频率控制输入产生同步时钟信号。 预定分辨率值是参考时钟信号的周期的1 / K（K是大于1的自然数）。 分频器频率分频同步时钟信号以产生分频时钟信号。

公开(公告)号：US20050141662A1

公开(公告)日：2005-06-30

申请号：US11020133

申请日：2004-12-27

申请人： Masaki Sano ,  Kinji Kayanuma

发明人： Masaki Sano ,  Kinji Kayanuma

IPC分类号： G11B20/10 ,  G11B20/14 ,  H03D3/24 ,  H03D13/00 ,  H03K5/00 ,  H03L7/06 ,  H03L7/08 ,  H03L7/085 ,  H03L7/087 ,  H03L7/099 ,  H04L7/033

CPC分类号： H03L7/087 ,  H03D13/003

摘要： A PLL circuit includes a phase comparing section, a low pass filter, a digital VCO circuit, and a frequency divider. The phase comparing section compares an inputted clock signal and a frequency-divided clock signal in phase to detect a phase difference. The low pass filter averages the phase difference outputted from the phase comparing section to output the averaged result as a frequency control input. The digital VCO circuit operates in synchronism with a reference clock signal, and generates a sync clock signal based on the frequency control input while a phase of the sync clock signal is controlled in units of predetermined resolution values. The predetermined resolution value is a 1/K (K is a natural number more than 1) of a period of the reference clock signal. The frequency divider frequency-divides the synch clock signal to generate the frequency-divided clock signal.

摘要翻译： PLL电路包括相位比较部分，低通滤波器，数字VCO电路和分频器。 相位比较部分将输入的时钟信号和分频时钟信号同相进行比较，以检测相位差。 低通滤波器对从相位比较部分输出的相位差进行平均，以将平均结果输出为频率控制输入。 数字VCO电路与参考时钟信号同步工作，并且在以预定分辨率值为单位控制同步时钟信号的相位时，基于频率控制输入产生同步时钟信号。 预定分辨率值是参考时钟信号的周期的1 / K（K是大于1的自然数）。 分频器频率分频同步时钟信号以产生分频时钟信号。

公开(公告)号：US06859106B2

公开(公告)日：2005-02-22

申请号：US10461389

申请日：2003-06-16

申请人： Masaki Sano

发明人： Masaki Sano

IPC分类号： G11B20/14 ,  H03K5/26 ,  H03L7/08 ,  H03L7/089 ,  H03L7/093 ,  H03L7/095 ,  H03L7/099 ,  H03L7/107 ,  H03L7/113 ,  H03L7/18 ,  H03L7/10

CPC分类号： H03L7/18 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/0996 ,  H03L7/113

摘要： A PLL circuit for comparing with a phase comparator 1a phase between an input signal and one of multiphase pulse signals CK0DIV to CKNDIV used as a channel clock generated by an output of a controlled oscillator 5, and controlling an oscillation of the controlled oscillator 5 according to a phase difference signal, comprises a frequency fixing circuit 9 for outputting an activating signal PCSTART for the control when the input signal is nearly equivalent to a frequency of the channel clock and has entered into a capture range of the phase comparator and a selection circuit 7 for selecting as the channel clock a multiphase pulse signal of a closest phase to a generating point of the input signal after generation of the activating signal, and the selection circuit 7 decides whether the input signal is advanced or delayed with respect to the channel clock after having selected a multiphase pulse signal as the channel clock and generates either an advance signal or delay signal according to the advance/delay of the input signal, for controlling a skew adjusting circuit 8 with the advance signal or delay signal.

摘要翻译： 一个PLL电路，用于与输入信号和用作由受控振荡器5的输出产生的通道时钟之间的多相脉冲信号CK0DIV至CKNDIV之一的相位比较器1a进行比较，并根据控制振荡器5的振荡来控制受控振荡器5的振荡。 相位差信号包括频率固定电路9，用于当输入信号几乎等于通道时钟的频率并且已经进入相位比较器的捕捉范围时输出用于控制的激活信号PCSTART和选择电路7 用于在产生激活信号之后选择与输入信号的生成点最接近的相位的多相脉冲信号，并且选择电路7判定输入信号是否相对于通道时钟而被提前或延迟 选择多相脉冲信号作为通道时钟，并根据t产生提前信号或延迟信号 o输入信号的提前/延迟，用于利用提前信号或延迟信号控制偏斜调整电路8。

公开(公告)号：US5398163A

公开(公告)日：1995-03-14

申请号：US86852

申请日：1993-07-07

申请人： Masaki Sano

发明人： Masaki Sano

IPC分类号： H05K1/02 ,  H05K1/00

CPC分类号： H05K1/0281 ,  H05K2201/055 ,  H05K2201/057 ,  H05K2201/09781 ,  H05K2201/2009

摘要： A flexible printed circuit board is provided including a flexible sheet having at least one electrically conductive layer, with a printed circuit pattern and a fold retainer pattern formed in one of the electrically conductive layers. The fold retainer pattern is electrically isolated from the printed circuit pattern. The fold retainer pattern has notches that indicate where the sheet is to be folded when the flexible sheet is folded, it is held in its folded shape by the fold retainer pattern.

摘要翻译： 提供了一种柔性印刷电路板，其包括具有至少一个导电层的柔性片，印刷电路图案和形成在一个导电层中的折叠保持器图案。 折叠保持器图案与印刷电路图案电隔离。 折叠保持器图案具有指示当柔性片材折叠时片材将被折叠的位置的凹口，其通过折叠保持器图案保持在折叠形状。

公开(公告)号：US4935821A

公开(公告)日：1990-06-19

申请号：US231395

申请日：1988-08-12

申请人： Masaki Sano ,  Yoshiaki Hanyu ,  Nobuharu Takahashi

发明人： Masaki Sano ,  Yoshiaki Hanyu ,  Nobuharu Takahashi

IPC分类号： H04N1/21 ,  H04N1/32 ,  H04N1/387 ,  H04N1/411

CPC分类号： H04N1/387 ,  H04N1/2175 ,  H04N1/32496 ,  H04N1/411

摘要： An image processing apparatus applicable to a multi-media copying machine with which multiple different recording media are usable includes a scanner for reading a document image and converting it into an electrical image signal, a floppy disk drive, an MPU and other controllers, and a printer for printing out an image on paper. The apparatus has not only a document-to-paper copying function but also a document-to-disk copying function and a disk-to-paper copying function.

摘要翻译： 可应用于可以使用多种不同记录介质的多媒体复印机的图像处理装置包括用于读取文件图像并将其转换为电子图像信号的扫描仪，软盘驱动器，MPU和其他控制器，以及 打印机用于在纸张上打印图像。 该设备不仅具有文件到纸张的复印功能，而且还具有文件到磁盘复制功能和磁盘到纸张的复印功能。

公开(公告)号：US4920942A

公开(公告)日：1990-05-01

申请号：US183127

申请日：1988-04-19

申请人： Kyoichi Fujimori ,  Masaki Sano

发明人： Kyoichi Fujimori ,  Masaki Sano

IPC分类号： F02D41/30 ,  F02M51/02 ,  F02M69/02 ,  F02M69/20

CPC分类号： F02M69/02 ,  F02D41/3082 ,  F02M51/02 ,  F02M69/20 ,  F02D2200/0602 ,  F02D2250/31

摘要： For supplying fuel from a fuel tank to an internal combustion engine by a fuel supply pump, a fuel delivery pressure of the fuel supply pump is regulated by a pressure regulating valve so as to maintain the difference between the fuel delivery pressure of the pump and an inner pressure of an intake manifold of the engine at a prescribed constant value, and the delivery volume of fuel from the pump is controlled in response to the fuel delivery pressure so as to minimize the amount of surplus fuel produced by the pressure regulating operation of the pressure regulating valve.

摘要翻译： 为了通过燃料供给泵从燃料箱向内燃机供给燃料，燃料供给泵的燃料输出压力由压力调节阀调节，以保持泵的燃料输出压力与 发动机的进气歧管的内压处于规定的常数值，并且响应于燃料输送压力来控制来自泵的燃料的输送量，以便将通过压力调节操作产生的剩余燃料的量最小化 调压阀。

公开(公告)号：US20080211589A1

公开(公告)日：2008-09-04

申请号：US12068813

申请日：2008-02-12

申请人： Masaki Sano

发明人： Masaki Sano

IPC分类号： H03L7/099

CPC分类号： H03L7/081 ,  H03L7/0994

摘要： A PLL circuit includes a polyphase reference clock output circuit, which outputs multiple reference clocks, each clock being of different phase. The PLL circuit further includes a digital voltage controlled oscillator, which, using any one of the multiple reference clocks chosen as an operating clock, outputs an output clock whose frequency varies according to a value of a frequency control signal, and which outputs a delay amount data representing a phase difference between the phase of the output clock and an ideal phase gained by computing based on the value of the frequency control signal. The PLL circuit further includes a selection circuit which is responsive to the delay amount data to select and output the output clock synchronized with one of the multiple reference clocks.

摘要翻译： PLL电路包括多相参考时钟输出电路，其输出多个参考时钟，每个时钟具有不同的相位。 PLL电路还包括数字压控振荡器，其使用选择为工作时钟的多个参考时钟中的任何一个，输出其频率根据频率控制信号的值而变化的输出时钟，并输出延迟量 数据表示输出时钟的相位与通过基于频率控制信号的值的计算而获得的理想相位之间的相位差。 PLL电路还包括响应于延迟量数据选择和输出与多个参考时钟中的一个同步的输出时钟的选择电路。

公开(公告)号：US07141442B2

公开(公告)日：2006-11-28

申请号：US10900321

申请日：2004-07-28

申请人： Masaki Sano

发明人： Masaki Sano

IPC分类号： H01L21/00 ,  H01L21/66

CPC分类号： H01L33/44 ,  H01L33/50 ,  H01L2224/48091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A method for manufacturing an LED device includes the steps of mounting an LED on a substrate, sealing the LED with a transparent resin including phosphor particles to form an LED device before being dyed, measuring chromaticity of light from the LED device before being dyed; and dyeing the sealing resin by a dye having a color for correcting the measured chromaticity to a desired color.