A PLL circuit includes a polyphase reference clock output circuit, which outputs multiple reference clocks, each clock being of different phase. The PLL circuit further includes a digital voltage controlled oscillator, which, using any one of the multiple reference clocks chosen as an operating clock, outputs an output clock whose frequency varies according to a value of a frequency control signal, and which outputs a delay amount data representing a phase difference between the phase of the output clock and an ideal phase gained by computing based on the value of the frequency control signal. The PLL circuit further includes a selection circuit which is responsive to the delay amount data to select and output the output clock synchronized with one of the multiple reference clocks.