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    VCO circuit, PLL circuit using VCO circuit, and data recording apparatus the PLL circuit
    1.
    发明授权
    VCO circuit, PLL circuit using VCO circuit, and data recording apparatus the PLL circuit 有权
    VCO电路，使用VCO电路的PLL电路和PLL电路的数据记录装置

    公开(公告)号：US07680235B2

    公开(公告)日：2010-03-16

    申请号：US11020133

    申请日：2004-12-27

    申请人： Masaki Sano ,  Kinji Kayanuma

    发明人： Masaki Sano ,  Kinji Kayanuma

    IPC分类号： H03D3/24

    CPC分类号： H03L7/087 ,  H03D13/003

    摘要： A PLL circuit includes a phase comparing section, a low pass filter, a digital VCO circuit, and a frequency divider. The phase comparing section compares an inputted clock signal and a frequency-divided clock signal in phase to detect a phase difference. The low pass filter averages the phase difference outputted from the phase comparing section to output the averaged result as a frequency control input. The digital VCO circuit operates in synchronism with a reference clock signal, and generates a sync clock signal based on the frequency control input while a phase of the sync clock signal is controlled in units of predetermined resolution values. The predetermined resolution value is a 1/K (K is a natural number more than 1) of a period of the reference clock signal. The frequency divider frequency-divides the synch clock signal to generate the frequency-divided clock signal.

    摘要翻译： PLL电路包括相位比较部分，低通滤波器，数字VCO电路和分频器。 相位比较部分将输入的时钟信号和分频时钟信号同相进行比较，以检测相位差。 低通滤波器对从相位比较部分输出的相位差进行平均，以将平均结果输出为频率控制输入。 数字VCO电路与参考时钟信号同步工作，并且在以预定分辨率值为单位控制同步时钟信号的相位时，基于频率控制输入产生同步时钟信号。 预定分辨率值是参考时钟信号的周期的1 / K（K是大于1的自然数）。 分频器频率分频同步时钟信号以产生分频时钟信号。

    VCO circuit, Pll circuit using VCO circuit, and data recording apparatus using the Pll circuit
    2.
    发明申请
    VCO circuit, Pll circuit using VCO circuit, and data recording apparatus using the Pll circuit 有权
    VCO电路，使用VCO电路的Pll电路，以及使用Pll电路的数据记录装置

    公开(公告)号：US20050141662A1

    公开(公告)日：2005-06-30

    申请号：US11020133

    申请日：2004-12-27

    申请人： Masaki Sano ,  Kinji Kayanuma

    发明人： Masaki Sano ,  Kinji Kayanuma

    IPC分类号： G11B20/10 ,  G11B20/14 ,  H03D3/24 ,  H03D13/00 ,  H03K5/00 ,  H03L7/06 ,  H03L7/08 ,  H03L7/085 ,  H03L7/087 ,  H03L7/099 ,  H04L7/033

    CPC分类号： H03L7/087 ,  H03D13/003

    摘要： A PLL circuit includes a phase comparing section, a low pass filter, a digital VCO circuit, and a frequency divider. The phase comparing section compares an inputted clock signal and a frequency-divided clock signal in phase to detect a phase difference. The low pass filter averages the phase difference outputted from the phase comparing section to output the averaged result as a frequency control input. The digital VCO circuit operates in synchronism with a reference clock signal, and generates a sync clock signal based on the frequency control input while a phase of the sync clock signal is controlled in units of predetermined resolution values. The predetermined resolution value is a 1/K (K is a natural number more than 1) of a period of the reference clock signal. The frequency divider frequency-divides the synch clock signal to generate the frequency-divided clock signal.

    摘要翻译： PLL电路包括相位比较部分，低通滤波器，数字VCO电路和分频器。 相位比较部分将输入的时钟信号和分频时钟信号同相进行比较，以检测相位差。 低通滤波器对从相位比较部分输出的相位差进行平均，以将平均结果输出为频率控制输入。 数字VCO电路与参考时钟信号同步工作，并且在以预定分辨率值为单位控制同步时钟信号的相位时，基于频率控制输入产生同步时钟信号。 预定分辨率值是参考时钟信号的周期的1 / K（K是大于1的自然数）。 分频器频率分频同步时钟信号以产生分频时钟信号。

    Phase locked loop circuit including digital voltage-controlled oscillator, ring oscillator and selector
    3.
    发明申请
    Phase locked loop circuit including digital voltage-controlled oscillator, ring oscillator and selector 有权
    锁相环电路包括数字压控振荡器，环形振荡器和选择器

    公开(公告)号：US20080211589A1

    公开(公告)日：2008-09-04

    申请号：US12068813

    申请日：2008-02-12

    申请人： Masaki Sano

    发明人： Masaki Sano

    IPC分类号： H03L7/099

    CPC分类号： H03L7/081 ,  H03L7/0994

    摘要： A PLL circuit includes a polyphase reference clock output circuit, which outputs multiple reference clocks, each clock being of different phase. The PLL circuit further includes a digital voltage controlled oscillator, which, using any one of the multiple reference clocks chosen as an operating clock, outputs an output clock whose frequency varies according to a value of a frequency control signal, and which outputs a delay amount data representing a phase difference between the phase of the output clock and an ideal phase gained by computing based on the value of the frequency control signal. The PLL circuit further includes a selection circuit which is responsive to the delay amount data to select and output the output clock synchronized with one of the multiple reference clocks.

    摘要翻译： PLL电路包括多相参考时钟输出电路，其输出多个参考时钟，每个时钟具有不同的相位。 PLL电路还包括数字压控振荡器，其使用选择为工作时钟的多个参考时钟中的任何一个，输出其频率根据频率控制信号的值而变化的输出时钟，并输出延迟量 数据表示输出时钟的相位与通过基于频率控制信号的值的计算而获得的理想相位之间的相位差。 PLL电路还包括响应于延迟量数据选择和输出与多个参考时钟中的一个同步的输出时钟的选择电路。

    Graphics processing apparatus for smoothing edges of images
    5.
    发明授权
    Graphics processing apparatus for smoothing edges of images 失效
    用于平滑图像边缘的图形处理装置

    公开(公告)号：US5357583A

    公开(公告)日：1994-10-18

    申请号：US914746

    申请日：1992-07-16

    申请人： Takashi Sato ,  Hiroki Kubozono ,  Hitomi Kumazaki ,  Masaki Sano ,  Kan Tomita ,  Yoshiaki Hanyu

    发明人： Takashi Sato ,  Hiroki Kubozono ,  Hitomi Kumazaki ,  Masaki Sano ,  Kan Tomita ,  Yoshiaki Hanyu

    IPC分类号： G06K15/12 ,  H04N1/409 ,  G06K9/00

    CPC分类号： H04N1/4092 ,  G06K15/1223

    摘要： A graphics processing apparatus includes a first detection part for detecting, with respect to each pixel of an image, whether or not an edge of the image starts on a scanline, and for setting a control data depending on whether or not the edge starts on the scanline, a second detection part for detecting a duration of beam power modulation corresponding to one or plural edge pixels being intersected by a line defined in the image, and for setting a duration data, a third detection part for detecting an outermost edge pixel in the edge pixels, a part for generating a beam power data indicating an intensity level of light beam power corresponding to the outermost edge pixel, an output part for outputting the image by means of a printer having a light source for emitting a light beam, and a control means for continuously modulating light beam power of the light source from the intensity level to a predetermined level with respect to the edge pixels, so that an image with smooth edges is generated by modulating the light beam power of the light source in accordance with the control data and the duration data.

    摘要翻译： 图形处理装置包括第一检测部分，用于相对于图像的每个像素检测图像的边缘是否在扫描线上开始，并且根据边缘是否开始在扫描线上开始来设置控制数据 扫描线，第二检测部分，用于检测对应于由图像中定义的线相交的一个或多个边缘像素的波束功率调制的持续时间，以及用于设置持续时间数据;第三检测部分，用于检测第一检测部分中的最外边缘像素 边缘像素，用于产生指示与最外边缘像素对应的光束功率的强度水平的光束功率数据的部分，用于通过具有用于发射光束的光源的打印机输出图像的输出部分，以及 用于将光源的光束功率从强度水平相对于边缘像素连续调制到预定水平的控制装置，使得具有平滑边缘的图像是 通过根据控制数据和持续时间数据调制光源的光束功率而产生。

    Clamp structure for plural members
    7.
    发明授权
    Clamp structure for plural members 失效
    多个成员的夹紧结构

    公开(公告)号：US5136760A

    公开(公告)日：1992-08-11

    申请号：US684814

    申请日：1991-04-15

    申请人： Masaki Sano ,  Norimichi Takahashi ,  Hidetaka Yokota

    发明人： Masaki Sano ,  Norimichi Takahashi ,  Hidetaka Yokota

    IPC分类号： G03B17/02 ,  F16B5/06 ,  H05K7/14

    CPC分类号： F16B5/0635 ,  H05K7/1417 ,  G03B2217/002 ,  Y10T24/44017 ,  Y10T24/44034 ,  Y10T403/76

    摘要： A clamp structure clamps superimposed circuit boards to a support plate portion of a rangefinder case in a still camera. The clamp structure includes first and second support arms spaced in confronting relation from each other by a distance greater than the thicknesses of the superimposed circuit boards and the support plate portion. The first and second support arms are disposed in sandwiching relation to the circuit boards and the support plate portion. A rod is inserted in a space defined between the second support arm and the lowermost circuit board which faces the second support arm while the first support arm is being held against the uppermost circuit board which faces the first support arm. With the rod inserted in the space, the circuit boards are fastened to the support plate portion between the first and second support arms under the resiliency of either an elastic member which is placed between the first support arm and the uppermost circuit board or the resiliency of the first and second support arms themselves.

    摘要翻译： 夹具结构将叠加的电路板夹在静止照相机中的测距仪壳体的支撑板部分上。 夹紧结构包括彼此面对的间隔开大于重叠电路板和支撑板部分的厚度的距离的第一和第二支撑臂。 第一和第二支撑臂以与电路板和支撑板部分夹持的方式设置。 当第一支撑臂被抵靠面对第一支撑臂的最上面的电路板时，杆被插入限定在第二支撑臂和最下面的电路板之间的与第二支撑臂相对的空间中。 当杆插入空间中时，电路板在放置在第一支撑臂和最上面的电路板之间的弹性构件的弹性下被固定到第一和第二支撑臂之间的支撑板部分，或者弹性 第一和第二支撑臂本身。

    PLASMA PROCESSING METHOD AND DEVICE ISOLATION METHOD
    8.
    发明申请
    PLASMA PROCESSING METHOD AND DEVICE ISOLATION METHOD 审中-公开
    等离子体处理方法和器件分离方法

    公开(公告)号：US20120252188A1

    公开(公告)日：2012-10-04

    申请号：US13432151

    申请日：2012-03-28

    申请人： Ryota YONEZAWA ,  Kazuyoshi Yamazaki ,  Masaki Sano

    发明人： Ryota YONEZAWA ,  Kazuyoshi Yamazaki ,  Masaki Sano

    IPC分类号： H01L21/762 ,  H01L21/318

    CPC分类号： H01L21/02247 ,  C23C8/36 ,  H01L21/02238 ,  H01L21/02326 ,  H01L21/02332 ,  H01L21/76224

    摘要： A plasma processing method for use in device isolation by shallow trench isolation in which an insulating film is embedded in a trench formed in silicon and the insulating film is planarized to form a device isolation film, the method includes a plasma nitriding the silicon of an inner wall surface of the trench by using a plasma before embedding the insulating film in the trench. The plasma nitriding is performed by using a plasma of a processing gas containing a nitrogen-containing gas under conditions in which a processing pressure ranges from 1.3 Pa to 187 Pa and a ratio of a volumetric flow rate of the nitrogen-containing gas to a volumetric flow rate of the entire processing gas ranges from 1% to 80% such that a silicon nitride film is formed on the inner wall surface of the trench to have a thickness of 1 to 10 nm.

    摘要翻译： 一种等离子体处理方法，用于通过浅沟槽隔离的器件隔离，其中将绝缘膜嵌入形成在硅中的沟槽中，并且绝缘膜被平坦化以形成器件隔离膜，该方法包括等离子体氮化内部的硅 在将绝缘膜嵌入沟槽中之前通过使用等离子体的沟槽的壁表面。 在处理压力为1.3Pa〜187Pa的条件下，通过使用含有含氮气体的处理气体的等离子体进行等离子体氮化，并且将含氮气体的体积流量与体积流量 整个处理气体的流量范围为1％至80％，使得在沟槽的内壁表面上形成厚度为1至10nm的氮化硅膜。

    PLL circuit and optical disc apparatus
    9.
    发明授权
    PLL circuit and optical disc apparatus 有权
    PLL电路和光盘装置

    公开(公告)号：US08258841B2

    公开(公告)日：2012-09-04

    申请号：US12773971

    申请日：2010-05-05

    申请人： Masaki Sano

    发明人： Masaki Sano

    IPC分类号： H03L7/06

    CPC分类号： H03L7/08 ,  H03L7/0991 ,  H03L7/16

    摘要： A PLL circuit includes a polyphase reference clock output circuit that outputs reference clocks, a polyphase frequency divider circuit that outputs divided clocks, which is obtained by dividing frequencies of the reference clocks, a selection switch circuit that selects one of the reference clocks or one of the divided clocks, and outputs the selected clock as a selected clock, a digital VCO that uses the selected clock as an operating clock, and outputs delay amount data indicating a phase difference between an output clock and an ideal phase, where the output clock has a frequency that fluctuates according to a value of frequency control input data, and the ideal phase is calculated according to the output clock and the value of the frequency control input data, and a selection circuit that selects and outputs the output clock synchronized with the divided clocks according to the delay amount data.

    摘要翻译： PLL电路包括输出参考时钟的多相基准时钟输出电路，输出分频时钟的多相分频电路，该分相时钟是通过对基准时钟的频率进行分频而获得的选择开关电路，选择开关电路选择参考时钟之一或者 分频时钟，并将所选择的时钟作为选择的时钟输出，使用所选择的时钟作为工作时钟的数字VCO，并输出指示输出时钟与理想相位之间的相位差的延迟量数据，其中输出时钟具有 根据频率控制输入数据的值而波动的频率，并且根据输出时钟和频率控制输入数据的值来计算理想相位;以及选择电路，其选择并输出与分频的同步的输出时钟 时钟根据延迟量数据。

    METHOD FOR IN-CHAMBER PREPROCESSING IN PLASMA NITRIDATION PROCESSING, PLASMA PROCESSING METHOD, AND PLASMA PROCESSING APPARATUS
    10.
    发明申请
    METHOD FOR IN-CHAMBER PREPROCESSING IN PLASMA NITRIDATION PROCESSING, PLASMA PROCESSING METHOD, AND PLASMA PROCESSING APPARATUS 审中-公开
    等离子体氮化处理中的室内预处理方法，等离子体处理方法和等离子体处理装置

    公开(公告)号：US20100239781A1

    公开(公告)日：2010-09-23

    申请号：US12601954

    申请日：2008-05-27

    申请人： Masaki Sano ,  Shuuichi Ishizuka

    发明人： Masaki Sano ,  Shuuichi Ishizuka

    IPC分类号： C23C16/44 ,  C23C16/00

    CPC分类号： H01L21/3143 ,  H01J37/32192 ,  H01J37/32477 ,  H01J37/32862 ,  H01L21/02332 ,  H01L21/28202 ,  H01L21/3115

    摘要： Disclosed is an in-chamber preprocessing method for carrying out preprocessing in a chamber prior to carrying out plasma nitridation processing of an oxide film, formed on a substrate, in the chamber. The method includes a step of supplying an oxygen-containing processing gas into the chamber and converting the gas into plasma, thereby generating an oxidizing plasma in the chamber (step 1), and a step of supplying a nitrogen-containing processing gas into the chamber and converting the gas into plasma, thereby generating a nitriding plasma in the chamber (step 2).

    摘要翻译： 公开了一种室内预处理方法，用于在室内形成的基板上进行氧化膜的等离子体氮化处理之前，在室内进行预处理。 该方法包括向室内供给含氧处理气体并将气体转化为等离子体的步骤，从而在室内产生氧化等离子体（步骤1），以及向室内供给含氮处理气体的工序 并将气体转化成等离子体，从而在室中产生氮化等离子体（步骤2）。