公开(公告)号：US09583430B2

公开(公告)日：2017-02-28

申请号：US14457094

申请日：2014-08-11

Applicant: Kyol Park ,  Jichul Kim ,  Yunhyeok Im ,  Eon Soo Jang

Inventor： Kyol Park ,  Jichul Kim ,  Yunhyeok Im ,  Eon Soo Jang

IPC: H01L23/538 ,  H01L23/522 ,  H01L23/552 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H05K1/02 ,  H05K1/14 ,  H01L25/065 ,  H01L23/42 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5385 ,  H01L23/552 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92225 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/0207 ,  H05K1/141 ,  H05K2201/10378 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The inventive concepts provide package-on-package (PoP) devices. In the PoP devices, an interposer substrate and a thermal boundary material layer may be disposed between a lower semiconductor package and an upper semiconductor package to rapidly exhaust heat generated from a lower semiconductor chip included in the lower semiconductor package. The interposer substrate may be formed of one or more insulating layers, conductive vias, heat dissipating members, protection layers, and various conductive patterns.

Abstract translation: 本发明的概念提供了封装封装（PoP）器件。 在PoP器件中，可以在下半导体封装和上半导体封装之间设置插入器衬底和热边界材料层，以快速排出由下半导体封装中包括的下半导体芯片产生的热。 插入器基板可以由一个或多个绝缘层，导电通孔，散热构件，保护层和各种导电图案形成。

公开(公告)号：US08587134B2

公开(公告)日：2013-11-19

申请号：US13587330

申请日：2012-08-16

Applicant: Yun-hyeok Im ,  Won-keun Kim ,  Tae-Je Cho ,  Kyol Park

Inventor： Yun-hyeok Im ,  Won-keun Kim ,  Tae-Je Cho ,  Kyol Park

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/367 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/10126 ,  H01L2224/10156 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83007 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/83887 ,  H01L2224/83888 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor package may include a substrate including a substrate pad on a top surface thereof; at least one semiconductor chip including a connection terminal electrically connected to the substrate on an active surface thereof, and mounted on the substrate; a heat release pattern formed between the substrate and the at least one semiconductor chip and configured to generate heat; and underfill resin underfilled between the substrate and the at least one semiconductor chip and comprising fillers. A semiconductor package may include a substrate including a substrate pad on a top surface thereof and a first heat release pattern configured to generate heat, and a semiconductor chip including a bonding pad formed on an active surface facing the substrate and a second heat release pattern configured to generate heat.

Abstract translation: 半导体封装可以包括在其顶表面上包括衬底焊盘的衬底; 至少一个半导体芯片，包括在其有源表面上电连接到所述衬底的连接端子，并且安装在所述衬底上; 形成在所述基板和所述至少一个半导体芯片之间并被配置为产生热量的散热图案; 以及在所述基底和所述至少一个半导体芯片之间未填充的底部填充树脂，并且包括填料。 半导体封装可以包括：衬底，其包括在其顶表面上的衬底焊盘和被配置为产生热量的第一散热图案;以及半导体芯片，其包括形成在与衬底相对的有源表面上的焊盘，以及第二散热图案， 产生热量。

公开(公告)号：US20140168902A1

公开(公告)日：2014-06-19

申请号：US14088482

申请日：2013-11-25

Applicant: Kyol PARK ,  Yun-Hyeok IM

Inventor： Kyol PARK ,  Yun-Hyeok IM

IPC: H05K1/02

CPC classification number: H01L23/3675 ,  H01L21/561 ,  H01L23/367 ,  H01L23/3677 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/8385 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0209 ,  H05K3/284 ,  H05K3/30 ,  H05K2201/0215 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package includes a circuit board having an inner circuit pattern and a plurality of contact pads connected to the inner circuit pattern, at least one integrated circuit (IC) device on the circuit board and making contact with the contact pads, a mold on the circuit board, the mold fixing the IC device to the circuit board, and a surface profile modifier on a surface of the IC device and a surface of the mold, and the surface profile modifier enlarging a surface area of the IC device and the mold to dissipate heat.

Abstract translation: 半导体封装包括具有内部电路图案和连接到内部电路图案的多个接触焊盘的电路板，电路板上的至少一个集成电路（IC）装置并与接触焊盘接触，模具在 电路板，将IC器件固定到电路板上的模具，以及IC器件表面和模具表面上的表面轮廓改性剂，以及将IC器件和模具的表面积扩大的表面轮廓修改器 散热

公开(公告)号：US20130134606A1

公开(公告)日：2013-05-30

申请号：US13587330

申请日：2012-08-16

Applicant: Yun-hyeok IM ,  Won-keun KIM ,  Tae-Je CHO ,  Kyol PARK

Inventor： Yun-hyeok IM ,  Won-keun KIM ,  Tae-Je CHO ,  Kyol PARK

IPC: H01L23/29 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/367 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/10126 ,  H01L2224/10156 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83007 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/83887 ,  H01L2224/83888 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor package may include a substrate including a substrate pad on a top surface thereof; at least one semiconductor chip including a connection terminal electrically connected to the substrate on an active surface thereof, and mounted on the substrate; a heat release pattern formed between the substrate and the at least one semiconductor chip and configured to generate heat; and underfill resin underfilled between the substrate and the at least one semiconductor chip and comprising fillers. A semiconductor package may include a substrate including a substrate pad on a top surface thereof and a first heat release pattern configured to generate heat, and a semiconductor chip including a bonding pad formed on an active surface facing the substrate and a second heat release pattern configured to generate heat.

Abstract translation: 半导体封装可以包括在其顶表面上包括衬底焊盘的衬底; 至少一个半导体芯片，包括在其有源表面上电连接到所述衬底的连接端子，并且安装在所述衬底上; 形成在所述基板和所述至少一个半导体芯片之间并被配置为产生热量的散热图案; 以及在所述基底和所述至少一个半导体芯片之间未填充的底部填充树脂，并且包括填料。 半导体封装可以包括：衬底，其包括在其顶表面上的衬底焊盘和被配置为产生热量的第一散热图案;以及半导体芯片，其包括形成在与衬底相对的有源表面上的焊盘，以及第二散热图案， 产生热量。

公开(公告)号：US09024434B2

公开(公告)日：2015-05-05

申请号：US13461949

申请日：2012-05-02

Applicant: Yunhyeok Im ,  Kyol Park ,  Taeje Cho

Inventor： Yunhyeok Im ,  Kyol Park ,  Taeje Cho

IPC: H01L23/34 ,  H01L23/12 ,  H01L23/373 ,  H01L23/36 ,  H01L23/31 ,  H01L23/427

CPC classification number: H01L23/36 ,  H01L23/3128 ,  H01L23/427 ,  H01L23/4275 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Semiconductor package are provided. In one embodiment, the semiconductor package may include a substrate such as a circuit substrate, a semiconductor chip mounted on the circuit substrate, a molding (or an encapsulant) covering the semiconductor chip and the circuit substrate and including a first temperature control member, and a heat dissipation member covering the molding.

Abstract translation: 提供半导体封装。 在一个实施例中，半导体封装可以包括诸如电路基板的基板，安装在电路基板上的半导体芯片，覆盖半导体芯片和电路基板并包括第一温度控制构件的模制件（或密封剂），以及 覆盖模制件的散热构件。

公开(公告)号：US09013031B2

公开(公告)日：2015-04-21

申请号：US14185394

申请日：2014-02-20

Applicant: Yunhyeok Im ,  Jichul Kim ,  Kyol Park ,  Seongho Shin

Inventor： Yunhyeok Im ,  Jichul Kim ,  Kyol Park ,  Seongho Shin

IPC: H01L23/02 ,  H01L23/36 ,  H01L23/34 ,  H01L23/48

CPC classification number: H01L23/34 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a lower package including a lower semiconductor chip on a lower package substrate, an upper package on the lower package, and a heat interface material between the lower package and the upper package. The upper package includes an upper semiconductor chip on an upper package substrate including a center portion adjacent to the lower semiconductor chip and an edge portion. The heat interface material is in contact with a top surface of the lower semiconductor chip and the upper package substrate. The upper package substrate includes a heat diffusion via penetrating the center portion and an interconnection via penetrating the edge portion. The interconnection via is spaced apart from the heat diffusion via.

Abstract translation: 半导体封装包括下封装，其包括在下封装基板上的下半导体芯片，下封装上的上封装，以及下封装和上封装之间的热界面材料。 上封装包括在上封装基板上的上半导体芯片，其包括与下半导体芯片相邻的中心部分和边缘部分。 热界面材料与下半导体芯片和上封装衬底的顶表面接触。 上封装衬底包括穿过中心部分的热扩散，以及穿过边缘部分的互连。 互连通孔与热扩散通孔间隔开。

公开(公告)号：US20150054148A1

公开(公告)日：2015-02-26

申请号：US14289900

申请日：2014-05-29

Applicant: Eon-Soo JANG ,  Kyol PARK ,  Jongwoo PARK ,  Jin-Kwon BAE ,  Yun-Hyeok IM ,  Ji-Chul KIM ,  Soojae PARK

Inventor： Eon-Soo JANG ,  Kyol PARK ,  Jongwoo PARK ,  Jin-Kwon BAE ,  Yun-Hyeok IM ,  Ji-Chul KIM ,  Soojae PARK

IPC: H01L23/34

CPC classification number: H01L23/49816 ,  H01L23/36 ,  H01L23/4334 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00

Abstract: According to example embodiments, a semiconductor package includes a lower package, upper packages on the lower package and laterally spaced apart from each other, a lower heat exhaust part between the lower package and the upper packages, an intermediate heat exhaust part between the upper packages and connected to the lower heat exhaust part, and an upper heat exhaust part on the upper packages and connected to the intermediate heat exhaust part.

Abstract translation: 根据示例实施例，半导体封装包括下封装，下封装上的上封装并且彼此横向间隔开，下封装和上封装之间的下热排出部分，位于上封装之间的中间热排出部 并连接到下部散热部，以及上部热封装上的上部散热部，并与中间散热部连接。

公开(公告)号：US20140339708A1

公开(公告)日：2014-11-20

申请号：US14243165

申请日：2014-04-02

Applicant: Eon Soo JANG ,  Kyol PARK ,  YUNHYEOK IM

Inventor： Eon Soo JANG ,  Kyol PARK ,  YUNHYEOK IM

IPC: H01L23/34 ,  H01L23/12 ,  H01L25/07

CPC classification number: H01L23/34 ,  H01L23/12 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/29194 ,  H01L2224/2929 ,  H01L2224/29309 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package device includes a lower package including a lower semiconductor chip mounted on the lower package substrate, a lower molding compound layer disposed on the lower package substrate, a first trench formed in the lower molding compound layer to surround the lower semiconductor chip, and a second trench connected to the first trench to extend to an outer wall of the lower package, the second trench being formed in the lower molding compound layer, an upper package disposed on the lower package. The upper package includes an upper package substrate and at least one upper semiconductor chip mounted on the upper package substrate and a heat transfer member disposed between the lower package and the upper package.

Abstract translation: 半导体封装器件包括下封装，其包括安装在下封装基板上的下半导体芯片，设置在下封装基板上的下模塑复合层，形成在下模塑复合层中以围绕下半导体芯片的第一沟槽，以及 连接到所述第一沟槽以延伸到所述下封装的外壁的第二沟槽，所述第二沟槽形成在所述下模塑复合层中，所述上封装设置在所述下封装上。 上封装包括上封装基板和安装在上封装基板上的至少一个上半导体芯片和设置在下封装和上封装之间的传热构件。

公开(公告)号：US09391009B2

公开(公告)日：2016-07-12

申请号：US14289900

申请日：2014-05-29

Applicant: Eon Soo Jang ,  Kyol Park ,  Jongwoo Park ,  Jin-Kwon Bae ,  Yunhyeok Im ,  Jichul Kim ,  Soojae Park

Inventor： Eon Soo Jang ,  Kyol Park ,  Jongwoo Park ,  Jin-Kwon Bae ,  Yunhyeok Im ,  Jichul Kim ,  Soojae Park

IPC: H01L23/36 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L23/433 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/36 ,  H01L23/4334 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00

Abstract: According to example embodiments, a semiconductor package includes a lower package, upper packages on the lower package and laterally spaced apart from each other, a lower heat exhaust part between the lower package and the upper packages, an intermediate heat exhaust part between the upper packages and connected to the lower heat exhaust part, and an upper heat exhaust part on the upper packages and connected to the intermediate heat exhaust part.

Abstract translation: 根据示例实施例，半导体封装包括下封装，下封装上的上封装并且彼此横向间隔开，下封装和上封装之间的下热排出部分，位于上封装之间的中间热排出部 并连接到下部散热部，以及上部热封装上的上部散热部，并与中间散热部连接。

公开(公告)号：US20150115467A1

公开(公告)日：2015-04-30

申请号：US14457094

申请日：2014-08-11

Applicant: Kyol PARK ,  JICHUL KIM ,  YUNHYEOK IM ,  Eon Soo JANG

Inventor： Kyol PARK ,  JICHUL KIM ,  YUNHYEOK IM ,  Eon Soo JANG

IPC: H01L23/522 ,  H05K1/02 ,  H05K1/11 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5385 ,  H01L23/552 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92225 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/0207 ,  H05K1/141 ,  H05K2201/10378 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The inventive concepts provide package-on-package (PoP) devices. In the PoP devices, an interposer substrate and a thermal boundary material layer may be disposed between a lower semiconductor package and an upper semiconductor package to rapidly exhaust heat generated from a lower semiconductor chip included in the lower semiconductor package. The interposer substrate may be formed of one or more insulating layers, conductive vias, heat dissipating members, protection layers, and various conductive patterns.

Abstract translation: 本发明的概念提供了封装封装（PoP）器件。 在PoP器件中，可以在下半导体封装和上半导体封装之间设置插入器衬底和热边界材料层，以快速排出由下半导体封装中包括的下半导体芯片产生的热。 插入器基板可以由一个或多个绝缘层，导电通孔，散热构件，保护层和各种导电图案形成。