公开(公告)号：US08487444B2

公开(公告)日：2013-07-16

申请号：US12631346

申请日：2009-12-04

Applicant: Oscar M. K. Law ,  Kuo H. Wu

Inventor： Oscar M. K. Law ,  Kuo H. Wu

IPC: H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/13099 ,  H01L2224/05552

Abstract: A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. A semiconductor die is manufactured with both via-first TSVs as well as via-last TSVs in order to establish low resistance paths for die connections between adjacent dies as well as for providing a low resistance path for feedthrough channels between multiple dies.

公开(公告)号：US08332794B2

公开(公告)日：2012-12-11

申请号：US12605209

申请日：2009-10-23

Applicant: Oscar M. K. Law ,  Kuo H. Wu

Inventor： Oscar M. K. Law ,  Kuo H. Wu

IPC: G06F17/50

CPC classification number: H03K19/17728 ,  G06F17/5054 ,  H03K19/17796

Abstract: A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other. The arrangement of the BTUs is subject to restricted design rules. Logical transistor units (LTUs) are formed from the BTUs using first and second layers of metallization. Methods for producing integrated circuits are disclosed forming programmable transistor arrays and implementing customer specified system designs upon the programmable transistor arrays.

Abstract translation: 公开了一种可编程晶体管阵列电路，包括半导体衬底; 以及以均匀间隔的单元的行和列排列的多个基本晶体管单元（BTU），所述BTU还包括PMOS晶体管单元（PTU），NMOS晶体管单元（NTU）和虚拟晶体管单元（DTU），每个BTU具有布置在其中的导体 通过BTU延伸的单个方向和导体相对于彼此均匀间隔开。 BTU的安排受限于设计规则。 逻辑晶体管单元（LTU）由使用第一和第二层金属化的BTU形成。 公开了用于制造集成电路的方法，其形成可编程晶体管阵列并且在可编程晶体管阵列上实现客户指定的系统

公开(公告)号：US20120290996A1

公开(公告)日：2012-11-15

申请号：US13559019

申请日：2012-07-26

Applicant: Oscar M. K. Law ,  Kuo H. Wu ,  Wei-Chih Yeh

Inventor： Oscar M. K. Law ,  Kuo H. Wu ,  Wei-Chih Yeh

IPC: G06F17/50

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/13023

Abstract: An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M1), wherein the plurality of metal lines couples the plurality of power TSVs to integrated circuit devices on the substrate.

Abstract translation: 集成电路结构包括具有基板和配电网的芯片。 所述配电网络包括贯穿所述基板的多个功率穿透硅通孔（TSV），其中所述多个功率TSV形成网格; 以及底部金属化层（M1）中的多个金属线，其中所述多个金属线将所述多个电源TSV耦合到所述衬底上的集成电路器件。

公开(公告)号：US08247906B2

公开(公告)日：2012-08-21

申请号：US12769334

申请日：2010-04-28

Applicant: Oscar M. K. Law ,  Kuo H. Wu ,  Wei-Chih Yeh

Inventor： Oscar M. K. Law ,  Kuo H. Wu ,  Wei-Chih Yeh

IPC: H01L23/48

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/13023

Abstract: An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M1), wherein the plurality of metal lines couples the plurality of power TSVs to integrated circuit devices on the substrate.

Abstract translation: 集成电路结构包括具有基板和配电网的芯片。 所述配电网络包括贯穿所述基板的多个功率穿透硅通孔（TSV），其中所述多个功率TSV形成网格; 以及底部金属化层（M1）中的多个金属线，其中所述多个金属线将所述多个电源TSV耦合到所述衬底上的集成电路器件。

公开(公告)号：US08264067B2

公开(公告)日：2012-09-11

申请号：US12838213

申请日：2010-07-16

Applicant: Oscar M. K. Law ,  Kuo H. Wu ,  Wei-Chih Yeh

Inventor： Oscar M. K. Law ,  Kuo H. Wu ,  Wei-Chih Yeh

IPC: H01L23/535

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L24/05 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

Abstract: A through silicon via architecture for integrated circuits is provided. The integrated circuit (IC) includes a substrate with a top surface and a bottom surface with circuitry formed on the top surface, a plurality of bonding pads formed along a periphery of the bottom surface, and a backside metal layer (BML) formed on the bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads. A first subset of bonding pads in the plurality of bonding pads is electrically coupled to circuitry on the top surface with through silicon vias (TSV). The BML distributes electrical signals provided by the second subset of bonding pads.

Abstract translation: 提供了一种用于集成电路的硅通孔架构。 集成电路（IC）包括具有顶表面和底表面的基板，其中电路形成在顶表面上，沿着底表面周边形成的多个接合焊盘和形成在底表面上的背侧金属层（BML） 并且电耦合到多个接合焊盘中的接合焊盘的第二子集。 多个接合焊盘中的接合焊盘的第一子集通过硅通孔（TSV）电耦合到顶表面上的电路。 BML分配由第二子接合焊盘提供的电信号。

公开(公告)号：US20120025388A1

公开(公告)日：2012-02-02

申请号：US12846418

申请日：2010-07-29

Applicant: Oscar M. K. LAW ,  Kuo H. WU

Inventor： Oscar M. K. LAW ,  Kuo H. WU

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/5286 ,  H01L24/16 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041

Abstract: A three dimensional (3D) integrated circuit (IC) structure having improved power and thermal management is described. The 3D IC structure includes at least first and second dies. Each of the first and second dies has at least one power through silicon via (TSV) and one signal TSV. The at least one power and signal TSVs of the first die are connected to the at least one power and signal TSVs of the second die, respectively. The 3D IC structure also includes one or more peripheral TSV structures disposed adjacent to one or more sides of the first and/or the second die. The peripheral TSV structures supply at least power and/or signals.

Abstract translation: 描述了具有改进的功率和热管理的三维（3D）集成电路（IC）结构。 3D IC结构至少包括第一和第二模具。 第一和第二管芯中的每一个具有通过硅通孔（TSV）和一个信号TSV的至少一个电力。 第一管芯的至少一个功率和信号TSV分别连接到第二管芯的至少一个功率和信号TSV。 3D IC结构还包括邻近第一和/或第二管芯的一个或多个侧面设置的一个或多个外围TSV结构。 外围TSV结构至少提供电源和/或信号。

公开(公告)号：US09026475B2

公开(公告)日：2015-05-05

申请号：US12581948

申请日：2009-10-20

Applicant: Kuo H. Wu

Inventor： Kuo H. Wu

IPC: G06Q10/06 ,  G06Q10/08 ,  G06Q10/10 ,  G06Q30/06 ,  G06F17/50 ,  G06Q20/10

CPC classification number: G06F17/5081 ,  G06Q10/101 ,  G06Q20/10

Abstract: A method for manufacturing integrated circuits (“ICs”) is disclosed. The method pertains to providing third-party technology in the form of an IC design library to foundry customers for designing IC products using alternate rule sets. Aggressive rules pertaining to IC layout are used to reduce device size, resulting in more device per wafer for the customer. The method includes a library creator creating a slim cell library, a slim cell library being provided to a customer to enable the customer to generate a slim IC design; an IC fabricator charging the customer a per-wafer premium to fabricate the slim IC design; the IC fabricator providing a first portion of the premium to a first entity, wherein the first entity is a contributor of technology for enabling creation of the slim cell library; and the IC fabricator providing a second portion of the premium to the library creator.

Abstract translation: 公开了一种用于制造集成电路（IC）的方法。 该方法涉及以IC设计库的形式提供第三方技术，以供代理客户使用备用规则集设计IC产品。 使用与IC布局相关的激进规则来减少设备尺寸，从而为客户提供更多的每个晶片设备。 该方法包括创建细长单元库的库创建器，提供给客户的细长单元库，以使客户能够生成超薄IC设计; 一个IC制造商向客户收取每晶圆溢价以制造超薄的IC设计; 所述IC制造者向所述第一实体提供所述溢价的第一部分，其中所述第一实体是能够创建所述超薄单元库的技术的贡献者; 并且IC制造商向图书馆创作者提供第二部分的保费。

公开(公告)号：US08552563B2

公开(公告)日：2013-10-08

申请号：US12652900

申请日：2010-01-06

Applicant: Oscar M. K. Law ,  Kuo H. Wu

Inventor： Oscar M. K. Law ,  Kuo H. Wu

IPC: H01L23/535

CPC classification number: H01L21/76898 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/5286 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/83 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. TSVs are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment this allows these connections to be made throughout the substrate instead of on the periphery of the substrate. In another embodiment, the TSVs are used as part of a power matrix to supply power and ground connections to the active devices and metallization layers through the substrate.

Abstract translation: 公开了一种用于通过硅通孔（TSV）制造半导体管芯连接的系统和方法。 TSV通过衬底形成，以允许信号连接以及电源和接地连接。 在一个实施例中，这允许在整个基板上进行这些连接，而不是在基板的外围。 在另一个实施例中，TSV被用作功率矩阵的一部分，以通过衬底向有源器件和金属化层提供电源和接地连接。

公开(公告)号：US08314635B2

公开(公告)日：2012-11-20

申请号：US12616985

申请日：2009-11-12

Applicant: Oscar M. K. Law ,  Kuo H. Wu

Inventor： Oscar M. K. Law ,  Kuo H. Wu

IPC: H01L25/00 ,  H01L21/70

CPC classification number: H01L27/0207 ,  G06F17/5045 ,  G06F17/5054 ,  G06F17/5068 ,  H01L25/18 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of designing integrated circuits includes providing a first chip and a second chip identical to each other. Each of the first chip and the second chip includes a base layer including a Logic Transistor Unit (LTU) array. The LTU array includes LTUs identical to each other and arranged in rows and columns. The method further includes connecting the base layer of the first chip to form a first application chip; and connecting the base layer of the second chip to form a second application chip different from the first application chip.

Abstract translation: 设计集成电路的方法包括提供彼此相同的第一芯片和第二芯片。 第一芯片和第二芯片中的每一个包括包括逻辑晶体管单元（LTU）阵列的基极层。 LTU阵列包括彼此相同并以行和列排列的LTU。 该方法还包括连接第一芯片的基层以形成第一应用芯片; 以及连接第二芯片的基层以形成与第一应用芯片不同的第二应用芯片。

公开(公告)号：US20110001249A1

公开(公告)日：2011-01-06

申请号：US12769334

申请日：2010-04-28

Applicant: Oscar M. K. Law ,  Kuo H. Wu ,  Wei-Chih Yeh

Inventor： Oscar M. K. Law ,  Kuo H. Wu ,  Wei-Chih Yeh

IPC: H01L23/52

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/13023

Abstract: An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M1), wherein the plurality of metal lines couples the plurality of power TSVs to integrated circuit devices on the substrate.

Abstract translation: 集成电路结构包括具有基板和配电网的芯片。 所述配电网络包括贯穿所述基板的多个功率穿透硅通孔（TSV），其中所述多个功率TSV形成网格; 以及底部金属化层（M1）中的多个金属线，其中所述多个金属线将所述多个电源TSV耦合到所述衬底上的集成电路器件。