A through silicon via architecture for integrated circuits is provided. The integrated circuit (IC) includes a substrate with a top surface and a bottom surface with circuitry formed on the top surface, a plurality of bonding pads formed along a periphery of the bottom surface, and a backside metal layer (BML) formed on the bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads. A first subset of bonding pads in the plurality of bonding pads is electrically coupled to circuitry on the top surface with through silicon vias (TSV). The BML distributes electrical signals provided by the second subset of bonding pads.