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    SEMICONDUCTOR DEVICES HAVING A FUSE AND METHODS OF CUTTING A FUSE
    2.
    发明申请
    SEMICONDUCTOR DEVICES HAVING A FUSE AND METHODS OF CUTTING A FUSE 审中-公开
    具有保险丝的半导体器件和切割保险丝的方法

    公开(公告)号：US20110212613A1

    公开(公告)日：2011-09-01

    申请号：US12912139

    申请日：2010-10-26

    Applicant: JEONG-KYU KIM ,  KUN-GU LEE

    Inventor： JEONG-KYU KIM ,  KUN-GU LEE

    IPC: H01L21/768

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device and methods of cutting a fuse of a semiconductor device are provided, the semiconductor device includes a semiconductor substrate that includes a fuse region, a plurality of fuse patterns disposed in the fuse region of the semiconductor substrate, and an insulating layer that insulates the fuse patterns from the semiconductor substrate. The fuse patterns each include a fuse. The fuse patterns are linked to the semiconductor substrate.

    Abstract translation: 提供半导体器件和切割半导体器件的熔丝的方法，半导体器件包括半导体衬底，其包括熔丝区域，设置在半导体衬底的熔丝区域中的多个熔丝图案，以及绝缘层， 来自半导体衬底的熔丝图案。 保险丝图案各自包括保险丝。 熔丝图案连接到半导体衬底。

    FUSE STRUCTURE OF A SEMICONDUCTOR DEVICE
    3.
    发明申请
    FUSE STRUCTURE OF A SEMICONDUCTOR DEVICE 审中-公开
    半导体器件的保险丝结构

    公开(公告)号：US20090302418A1

    公开(公告)日：2009-12-10

    申请号：US12478365

    申请日：2009-06-04

    Applicant: Hyun-Soo CHUNG ,  Dong-Ho LEE ,  Dong-Hyeon JANG ,  Eun-Chul AHN ,  Kun-Gu LEE ,  Chang-Woo SHIN

    Inventor： Hyun-Soo CHUNG ,  Dong-Ho LEE ,  Dong-Hyeon JANG ,  Eun-Chul AHN ,  Kun-Gu LEE ,  Chang-Woo SHIN

    IPC: H01L23/525

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided is a fuse structure of a semiconductor device. The fuse structure may include an insulating layer pattern structure, a fuse and a protecting layer pattern. The insulating layer pattern structure may be formed on a substrate. The insulating layer pattern structure may have an opening. The fuse may be formed in the opening. The protecting layer pattern may be formed in the opening of the insulating layer pattern structure to cover the fuse.

    Abstract translation: 提供半导体器件的熔丝结构。 熔丝结构可以包括绝缘层图案结构，熔丝和保护层图案。 绝缘层图案结构可以形成在基板上。 绝缘层图案结构可以具有开口。 保险丝可以形成在开口中。 保护层图案可以形成在绝缘层图案结构的开口中以覆盖保险丝。

    Semiconductor device having fuse pattern and methods of fabricating the same
    4.
    发明授权
    Semiconductor device having fuse pattern and methods of fabricating the same 失效
    具有熔丝图案的半导体器件及其制造方法

    公开(公告)号：US07556989B2

    公开(公告)日：2009-07-07

    申请号：US11387158

    申请日：2006-03-22

    Applicant: Tai-Heui Cho ,  Kun-Gu Lee

    Inventor： Tai-Heui Cho ,  Kun-Gu Lee

    IPC: H01L21/82 ,  H01L21/311

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern, and a second insulating layer formed on the first insulating layer and covering the fuse pattern.

    Abstract translation: 半导体器件包括具有熔丝区域和互连区域的半导体衬底，形成在熔丝区域和互连区域中的第一绝缘层，形成在熔丝区域中的第一绝缘层上的熔丝图案，熔丝图案包括第一 导电图案和第一封盖图案，形成在互连区域中的第一绝缘层上的互连图案，包括第二导电图案和第二封盖图案，并且具有大于熔丝图案的厚度的厚度，以及第二绝缘体 层，形成在第一绝缘层上并覆盖熔丝图案。

    SEMICONDUCTOR DEVICE HAVING FUSE PATTERN AND METHODS OF FABRICATING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE HAVING FUSE PATTERN AND METHODS OF FABRICATING THE SAME 审中-公开
    具有保险丝图案的半导体器件及其制造方法

    公开(公告)号：US20090236688A1

    公开(公告)日：2009-09-24

    申请号：US12478583

    申请日：2009-06-04

    Applicant: Tai-Heui CHO ,  Kun-Gu LEE

    Inventor： Tai-Heui CHO ,  Kun-Gu LEE

    IPC: H01L23/525

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern, and a second insulating layer formed on the first insulating layer and covering the fuse pattern.

    Abstract translation: 半导体器件包括具有熔丝区域和互连区域的半导体衬底，形成在熔丝区域和互连区域中的第一绝缘层，形成在熔丝区域中的第一绝缘层上的熔丝图案，熔丝图案包括第一 导电图案和第一封盖图案，形成在互连区域中的第一绝缘层上的互连图案，包括第二导电图案和第二封盖图案，并且具有大于熔丝图案的厚度的厚度，以及第二绝缘体 层，形成在第一绝缘层上并覆盖熔丝图案。

    Fuse box reducing damage caused by laser blowing and cross talk, and method of manufacturing the same
    7.
    发明申请
    Fuse box reducing damage caused by laser blowing and cross talk, and method of manufacturing the same 失效
    保险丝盒减少由激光吹扫和串扰引起的损坏及其制造方法

    公开(公告)号：US20070152297A1

    公开(公告)日：2007-07-05

    申请号：US11637996

    申请日：2006-12-13

    Applicant: Kwang-kyu Bang ,  Kun-gu Lee ,  Jeong-kyu Kim

    Inventor： Kwang-kyu Bang ,  Kun-gu Lee ,  Jeong-kyu Kim

    IPC: H01L29/00

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided are a fuse box that simultaneously prevents damage caused by laser blowing and cross talk between the fuses and a method of manufacturing the same. In a fuse box having an open region in which fuses are opened by laser blowing and a bundle region in which fuse opens do not occur, a capping layer, adjacent to the open region, having a metal layer and an insulation layer covers the outermost fuses in the bundle region, thereby reducing the influence of laser blowing of fuses in the bundle region, and preventing capacitive coupling caused by the formation of a parasitic capacitor between fuse lines and an insulation layer therebetween. Accordingly, cross talk due to the capacitive coupling can be prevented, thereby enhancing the reliability of a fuse circuit. Lower fuses can be disposed in a lower layer in the bundle region, thereby forming a two-layered fuse box.

    Abstract translation: 提供了一种保险丝盒，其同时防止由熔断器之间的激光吹扫和串扰造成的损坏及其制造方法。 在具有开放区域的保险丝盒中，通过激光吹制保险丝打开，并且不会发生保险丝打开的束区域，具有金属层和绝缘层的与敞开区域相邻的封盖层覆盖最外侧保险丝 在束区域中，由此减少了束区域中的熔丝的激光吹送的影响，并且防止了熔丝线之间的寄生电容器之间形成的电容耦合以及它们之间的绝缘层。 因此，可以防止由于电容耦合引起的串扰，从而提高了熔丝电路的可靠性。 下部保险丝可以设置在束区域的下层中，从而形成双层保险丝盒。

    Fuse box reducing damage caused by laser blowing and cross talk
    8.
    发明授权
    Fuse box reducing damage caused by laser blowing and cross talk 失效
    保险丝盒减少了激光吹扫和串扰造成的损坏

    公开(公告)号：US07605444B2

    公开(公告)日：2009-10-20

    申请号：US11637996

    申请日：2006-12-13

    Applicant: Kwang-kyu Bang ,  Kun-gu Lee ,  Jeong-kyu Kim

    Inventor： Kwang-kyu Bang ,  Kun-gu Lee ,  Jeong-kyu Kim

    IPC: H01L29/00

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided are a fuse box that simultaneously prevents damage caused by laser blowing and cross talk between the fuses and a method of manufacturing the same. In a fuse box having an open region in which fuses are opened by laser blowing and a bundle region in which fuse opens do not occur, a capping layer, adjacent to the open region, having a metal layer and an insulation layer covers the outermost fuses in the bundle region, thereby reducing the influence of laser blowing of fuses in the bundle region, and preventing capacitive coupling caused by the formation of a parasitic capacitor between fuse lines and an insulation layer therebetween. Accordingly, cross talk due to the capacitive coupling can be prevented, thereby enhancing the reliability of a fuse circuit. Lower fuses can be disposed in a lower layer in the bundle region, thereby forming a two-layered fuse box.

    Abstract translation: 提供了一种保险丝盒，其同时防止由熔断器之间的激光吹扫和串扰造成的损坏及其制造方法。 在具有开放区域的保险丝盒中，通过激光吹制保险丝打开，并且不会发生保险丝打开的束区域，具有金属层和绝缘层的与敞开区域相邻的封盖层覆盖最外侧保险丝 在束区域中，由此减少了束区域中的熔丝的激光吹送的影响，并且防止了熔丝线之间的寄生电容器之间形成的电容耦合以及它们之间的绝缘层。 因此，可以防止由于电容耦合引起的串扰，从而提高了熔丝电路的可靠性。 下部保险丝可以设置在束区域的下层中，从而形成双层保险丝盒。

    REFERENCE WAFER FOR CALIBRATING SEMICONDUCTOR EQUIPMENT
    9.
    发明申请
    REFERENCE WAFER FOR CALIBRATING SEMICONDUCTOR EQUIPMENT 审中-公开
    用于校准半导体设备的参考波形

    公开(公告)号：US20070037078A1

    公开(公告)日：2007-02-15

    申请号：US11463826

    申请日：2006-08-10

    Applicant: Kun-Gu LEE ,  Ki-Ho SEONG ,  Yoo-Mi LEE

    Inventor： Kun-Gu LEE ,  Ki-Ho SEONG ,  Yoo-Mi LEE

    IPC: G03C5/00

    CPC classification number: G01R31/318511 ,  G01R31/2831 ,  G01R31/3193

    Abstract: A reference wafer for calibrating a laser and a camera and checking laser accuracy and spot size. The reference wafer may include a light absorption layer on a semiconductor substrate and a light reflection layer pattern on the light absorption layer. The light reflection layer pattern may include a first pattern for checking the laser accuracy and spot size and a second pattern for calibrating the laser and camera. A first anti-reflective layer may be introduced between the light absorption layer and the semiconductor substrate, and a second anti-reflective layer may be introduced between the light absorption layer and the light reflection layer pattern.

    Abstract translation: 用于校准激光和相机的参考晶片，并检查激光精度和光斑尺寸。 参考晶片可以包括半导体衬底上的光吸收层和光吸收层上的光反射层图案。 光反射层图案可以包括用于检查激光精度和光斑尺寸的第一图案和用于校准激光和照相机的第二图案。 可以在光吸收层和半导体衬底之间引入第一抗反射层，并且可以在光吸收层和光反射层图案之间引入第二抗反射层。

    Semiconductor device having fuse pattern and methods of fabricating the same
    10.
    发明申请
    Semiconductor device having fuse pattern and methods of fabricating the same 失效

    公开(公告)号：US20060214260A1

    公开(公告)日：2006-09-28

    申请号：US11387158

    申请日：2006-03-22

    Applicant: Tai-Heui Cho ,  Kun-Gu Lee

    Inventor： Tai-Heui Cho ,  Kun-Gu Lee

    IPC: H01L29/00

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern, and a second insulating layer formed on the first insulating layer and covering the fuse pattern.

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