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    Test apparatus having multiple head boards at one handler and its test method
    1.
    发明授权
    Test apparatus having multiple head boards at one handler and its test method 有权
    在一个处理机上具有多个头板的测试装置及其测试方法

    公开(公告)号：US07602172B2

    公开(公告)日：2009-10-13

    申请号：US12109299

    申请日：2008-04-24

    Applicant: Ae-Yong Chung ,  Sung-Ok Kim ,  Kyeong-Seon Shin ,  Jeong-Ho Bang

    Inventor： Ae-Yong Chung ,  Sung-Ok Kim ,  Kyeong-Seon Shin ,  Jeong-Ho Bang

    IPC: G01R31/26

    CPC classification number: G01R31/2893 ,  G01R31/01 ,  G01R31/2851

    Abstract: A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.

    Abstract translation: 测试装置包括连接到测试器的一个处理器和分成两个或更多个站点或两个或更多个测试板的一个测试板。 由于只有测试板（或测试板）上的站点需要复制，而不是处理器的加载通道或分拣机，所以测试设备可以方便地紧凑。 此外，在一个站点或一个测试板上测试半导体器件时，可以根据测试结果对另一个站点中的另一个站点或另一个测试板上的半导体器件进行分类。 这使得能够减少或消除测试器空闲时间以优化测试设备的效率。

    TEST SYSTEM OF SEMICONDUCTOR DEVICE HAVING A HANDLER REMOTE CONTROL AND METHOD OF OPERATING THE SAME
    2.
    发明申请
    TEST SYSTEM OF SEMICONDUCTOR DEVICE HAVING A HANDLER REMOTE CONTROL AND METHOD OF OPERATING THE SAME 有权
    具有操作者远程控制的半导体器件的测试系统及其操作方法

    公开(公告)号：US20070290707A1

    公开(公告)日：2007-12-20

    申请号：US11749053

    申请日：2007-05-15

    Applicant: Ae-Yong CHUNG ,  Eun-Seok LEE ,  Jeong-Ho BANG ,  Kyeong-Seon SHIN ,  Dae-Gab CHI ,  Sung-Ok KIM

    Inventor： Ae-Yong CHUNG ,  Eun-Seok LEE ,  Jeong-Ho BANG ,  Kyeong-Seon SHIN ,  Dae-Gab CHI ,  Sung-Ok KIM

    IPC: G01R31/00

    CPC classification number: G01R31/2893 ,  G01R31/2894 ,  G01R31/31718 ,  G01R31/31919

    Abstract: A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.

    Abstract translation: 提供了一种用于处理器遥控器的半导体器件的测试系统。 该系统包括：用于测试半导体器件的测试仪; 通过GPIB（通用指令总线）通信电缆连接到测试仪的处理器; 连接到测试器的测试仪服务器向测试者下载测试程序，处理程序遥控程序和处理程序状态检查程序; 以及通过GPIB通信电缆在测试者和处理者之间发送和接收的通信数据，其中通信数据具有用于半导体器件的电气测试的基本通信数据，用于处理器远程控制的通信数据和用于处理器状态的通信数据 检查。

    Flash memory test system and method capable of test time reduction
    3.
    发明授权
    Flash memory test system and method capable of test time reduction 失效
    闪存测试系统和方法能够测试时间缩短

    公开(公告)号：US07254757B2

    公开(公告)日：2007-08-07

    申请号：US10954834

    申请日：2004-09-29

    Applicant: Dong-Kyoo Park ,  Jong-Kook Kim ,  Jeong-Ho Bang ,  Sang-Young Choi ,  Eun-Sik Kim

    Inventor： Dong-Kyoo Park ,  Jong-Kook Kim ,  Jeong-Ho Bang ,  Sang-Young Choi ,  Eun-Sik Kim

    IPC: G11C29/00 ,  G11C7/00 ,  G01R31/28

    CPC classification number: G11C29/56004 ,  G11C29/56 ,  G11C2029/2602

    Abstract: A flash memory test system capable of test time reduction and an electrical test method using the same: The invention provides a parallel tester that includes a first memory and a second memory. The first and second memories are used to each supply different data to identical addresses within a plurality of DUTs, thereby making it possible to conduct in parallel tests such as trim tests, repair tests, and invalid block masking test. Thus parallel testing is done to replace testing that was previously done serially.

    Abstract translation: 一种能够测试时间缩短的闪存测试系统和使用其的电测试方法。本发明提供一种包括第一存储器和第二存储器的并行测试器。 第一和第二存储器用于将不同的数据提供给多个DUT中的相同地址，从而使得可以在并行测试中进行诸如修整测试，修复测试和无效块掩蔽测试。 因此，进行并行测试来替代以前连续完成的测试。

    Apparatus and method for performing parallel test on integrated circuit devices
    5.
    发明申请
    Apparatus and method for performing parallel test on integrated circuit devices 有权
    在集成电路设备上执行并行测试的装置和方法

    公开(公告)号：US20050007140A1

    公开(公告)日：2005-01-13

    申请号：US10856461

    申请日：2004-05-27

    Applicant: Woo-Il Kim ,  Hyun-Seop Shim ,  Hyoung-Young Lee ,  Young-Ki Kwak ,  Jeong-Ho Bang ,  Ki-Bong Ju

    Inventor： Woo-Il Kim ,  Hyun-Seop Shim ,  Hyoung-Young Lee ,  Young-Ki Kwak ,  Jeong-Ho Bang ,  Ki-Bong Ju

    IPC: G01R31/28 ,  G01R31/319 ,  G11C29/00 ,  G01R31/26

    CPC classification number: G01R31/31905 ,  G11C2029/2602

    Abstract: Embodiments of the invention connect a plurality of devices under test (DUTS) in a parallel manner and a high test current is selectively applied to each DUT. The apparatus to test a plurality of DUTs includes a plurality of power sources providing the test current to a plurality of DUTs; and switching devices connected to the respective DUTs and power sources and selectively providing the test current. In addition, the apparatus has at least one control unit to control the switching devices. Furthermore, a group of DUTs from the plurality of DUTs is connected between two of the plurality of power sources in a parallel manner, and the test current is selectively provided to one DUT from the group of DUTs according to the operation of the switching devices.

    Abstract translation: 本发明的实施例以并行方式连接多个待测器件（DUTS），并且将高测试电流选择性地施加到每个DUT。 测试多个DUT的装置包括向多个DUT提供测试电流的多个电源; 以及连接到各个DUT和电源的开关装置，并选择性地提供测试电流。 此外，该装置具有至少一个控制单元来控制开关装置。 此外，来自多个DUT的一组DUT以并行方式连接在多个电源中的两个之间，并且根据开关装置的操作，从DUT组中选择性地向一个DUT提供测试电流。

    Plasma display panel apparatus and method of protecting an over current thereof
    6.
    发明授权
    Plasma display panel apparatus and method of protecting an over current thereof 失效
    等离子显示面板装置及其过电流保护方法

    公开(公告)号：US06710550B2

    公开(公告)日：2004-03-23

    申请号：US10183526

    申请日：2002-06-28

    Applicant: Jeong-ho Bang

    Inventor： Jeong-ho Bang

    IPC: G09G310

    CPC classification number: G09G3/2965 ,  G09G2330/025 ,  G09G2330/04

    Abstract: A plasma display panel apparatus includes a pair of discharge sustaining electrodes, a panel capacitor to supply charged voltage alternately to each electrode of the pair of discharge sustaining electrodes, a switching device for discharge that is turned on when the panel capacitor is discharged, to thereby pass through discharged current of the panel capacitor, a current sensing part to sense the current passed through by the switching device for discharge, and an over-current controlling part that turns off the switching device for discharge when the current sensed in the current sensing part is at or above a predetermined reference value. With this configuration, the plasma display panel apparatus protects the switching device from over-current generated during an abnormal driving of the discharge sustaining electrode driving circuit.

    Abstract translation: 等离子体显示面板装置包括一对放电维持电极，对一对放电维持电极的每个电极交替地提供充电电压的面板电容器，当面板电容器放电时导通的用于放电的开关装置，从而 通过面板电容器的放电电流，电流检测部分，用于感测由开关装置进行放电的电流;以及过电流控制部，当在电流感测部分中感测到的电流时，切断装置进行放电 处于或高于预定的参考值。 利用这种配置，等离子体显示面板装置保护开关装置免于在放电维持电极驱动电路的异常驱动期间产生的过电流。

    TEST APPARATUS HAVING MULTIPLE TEST SITES AT ONE HANDLER AND ITS TEST METHOD
    7.
    发明申请
    TEST APPARATUS HAVING MULTIPLE TEST SITES AT ONE HANDLER AND ITS TEST METHOD 有权
    具有多个测试站点的测试设备及其测试方法

    公开(公告)号：US20080197874A1

    公开(公告)日：2008-08-21

    申请号：US12109299

    申请日：2008-04-24

    Applicant: Ae-Yong CHUNG ,  Sung-Ok KIM ,  Kyeong-Seon SHIN ,  Jeong-Ho BANG

    Inventor： Ae-Yong CHUNG ,  Sung-Ok KIM ,  Kyeong-Seon SHIN ,  Jeong-Ho BANG

    IPC: G01R31/26

    CPC classification number: G01R31/2893 ,  G01R31/01 ,  G01R31/2851

    Abstract: A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.

    Abstract translation: 测试装置包括连接到测试器的一个处理器和分成两个或更多个站点或两个或更多个测试板的一个测试板。 由于只有测试板（或测试板）上的站点需要复制，而不是处理器的加载通道或分拣机，所以测试设备可以方便地紧凑。 此外，在一个站点或一个测试板上测试半导体器件时，可以根据测试结果对另一个站点中的另一个站点或另一个测试板上的半导体器件进行分类。 这使得能够减少或消除测试器空闲时间以优化测试设备的效率。

    Test system of semiconductor device having a handler remote control and method of operating the same
    8.
    发明授权
    Test system of semiconductor device having a handler remote control and method of operating the same 有权
    具有处理器遥控器的半导体器件的测试系统及其操作方法

    公开(公告)号：US07408339B2

    公开(公告)日：2008-08-05

    申请号：US11749053

    申请日：2007-05-15

    Applicant: Ae-Yong Chung ,  Eun-Seok Lee ,  Jeong-Ho Bang ,  Kyeong-Seon Shin ,  Dae-Gab Chi ,  Sung-Ok Kim

    Inventor： Ae-Yong Chung ,  Eun-Seok Lee ,  Jeong-Ho Bang ,  Kyeong-Seon Shin ,  Dae-Gab Chi ,  Sung-Ok Kim

    IPC: G01R31/28

    CPC classification number: G01R31/2893 ,  G01R31/2894 ,  G01R31/31718 ,  G01R31/31919

    Abstract: A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.

    Abstract translation: 提供了一种用于处理器遥控器的半导体器件的测试系统。 该系统包括：用于测试半导体器件的测试仪; 通过GPIB（通用指令总线）通信电缆连接到测试仪的处理器; 连接到测试器的测试仪服务器向测试者下载测试程序，处理程序遥控程序和处理程序状态检查程序; 以及通过测试者和处理者之间的GPIB通信电缆发送和接收的通信数据，其中通信数据具有用于半导体器件的电气测试的基本通信数据，用于处理器远程控制的通信数据和用于处理器状态的通信数据 检查。

    Test apparatus having multiple test sites at one handler and its test method
    9.
    发明授权
    Test apparatus having multiple test sites at one handler and its test method 有权
    在一个处理机上具有多个测试点的测试设备及其测试方法

    公开(公告)号：US07378864B2

    公开(公告)日：2008-05-27

    申请号：US11092067

    申请日：2005-03-28

    Applicant: Ae-Yong Chung ,  Sung-Ok Kim ,  Kyeong-Seon Shin ,  Jeong-Ho Bang

    Inventor： Ae-Yong Chung ,  Sung-Ok Kim ,  Kyeong-Seon Shin ,  Jeong-Ho Bang

    IPC: G01R31/26 ,  G01R31/28

    CPC classification number: G01R31/2893 ,  G01R31/01 ,  G01R31/2851

    Abstract: A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.

    Abstract translation: 测试装置包括连接到测试器的一个处理器和分成两个或更多个站点或两个或更多个测试板的一个测试板。 由于只有测试板（或测试板）上的站点需要复制，而不是处理器的加载通道或分拣机，所以测试设备可以方便地紧凑。 此外，在一个站点或一个测试板上测试半导体器件时，可以根据测试结果对另一个站点中的另一个站点或另一个测试板上的半导体器件进行分类。 这使得能够减少或消除测试器空闲时间以优化测试设备的效率。

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