公开(公告)号：US07804153B2

公开(公告)日：2010-09-28

申请号：US11843777

申请日：2007-08-23

Applicant: Kwang-kyu Bang ,  Jun-ho Jang ,  Yoo-mi Lee

Inventor： Kwang-kyu Bang ,  Jun-ho Jang ,  Yoo-mi Lee

IPC: H01L23/62

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a fuse structure that can prevent a bridge between a fuse pattern and a guard ring, and a method of fabricating the same are provided. The fuse pattern formed on a multiple-layered metal interconnect layer is stepped shape increasing a vertical distance between the fuse pattern and the guard ring.

Abstract translation: 具有可以防止熔丝图案和保护环之间的桥接的熔丝结构的半导体器件及其制造方法。 形成在多层金属互连层上的熔丝图形是增加熔丝图案和保护环之间的垂直距离的阶梯形状。

公开(公告)号：US07516426B2

公开(公告)日：2009-04-07

申请号：US11561537

申请日：2006-11-20

Applicant: Terence B. Hook ,  Jeffrey B. Johnson ,  Yoo-Mi Lee

Inventor： Terence B. Hook ,  Jeffrey B. Johnson ,  Yoo-Mi Lee

IPC: G06F17/50

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L27/0207

Abstract: Methods of improving operational parameters between at least a pair of matched transistors, and a set of transistors, are disclosed. One embodiment of a method includes a method of improving at least one of a threshold voltage (Vt) mismatch and current drive between at least a pair of matched transistors for analog applications, the method comprising: forming at least a pair of transistors, each with a gate having a plurality of connected fingers; and optimizing a total length of a channel under the plurality of fingers to attain at least one of: a) a reduced threshold voltage mismatch between the at least pair of transistors, and b) increased current drive for a given threshold voltage mismatch, between the at least pair of transistors, each finger having a length less than an overall length of the channel.

Abstract translation: 公开了改善至少一对匹配晶体管之间的操作参数的方法和一组晶体管。 方法的一个实施例包括一种改进用于模拟应用的至少一对匹配晶体管之间的阈值电压（Vt）失配和电流驱动中的至少一个的方法，所述方法包括：形成至少一对晶体管，每个晶体管具有 具有多个连接的手指的门; 以及优化所述多个指状物下的通道的总长度以达到以下至少一个：a）所述至少一对晶体管之间的阈值电压失配降低，以及b）对于给定阈值电压失配的增加的电流驱动， 至少一对晶体管，每个手指的长度小于通道的总长度。

公开(公告)号：US07640143B2

公开(公告)日：2009-12-29

申请号：US10904307

申请日：2004-11-03

Applicant: Calvin J. Bittner ,  Steven A. Grundon ,  Yoo-Mi Lee ,  Ning Lu ,  Josef S. Watts

Inventor： Calvin J. Bittner ,  Steven A. Grundon ,  Yoo-Mi Lee ,  Ning Lu ,  Josef S. Watts

IPC: G06F17/10 ,  G06F17/50

CPC classification number: G06F17/5036

Abstract: A method, system and program product are disclosed for statistical modeling an integrated circuit that provides information about partial correlations between model parameters. The invention determines a variance-covariance matrix for data to be modeled; conducts principal component analysis on the variance-covariance matrix; and creates a statistical model with an independent distribution for each principal component, allowing calculation of each individual model parameter as a weighted sum by a circuit simulator. The statistical model provides information about how well individual transistors will track one another based on layout similarity. This allows the designer to quantify and take advantage of design practices that make all transistors similar, for example, by orienting all gates in the same direction. A method, system and program product for simulating a circuit using the statistical model are also included.

Abstract translation: 公开了一种用于统计建模集成电路的方法，系统和程序产品，其提供关于模型参数之间的部分相关性的信息。 本发明确定要建模的数据的方差 - 协方差矩阵; 对方差协方差矩阵进行主成分分析; 并为每个主成分创建一个具有独立分布的统计模型，允许通过电路模拟器计算每个单独的模型参数作为加权和。 统计模型提供了有关单个晶体管基于布局相似性将彼此跟踪的信息。 这允许设计者量化并利用使所有晶体管相似的设计实践，例如通过将所有栅极定向在相同的方向。 还包括用于使用统计模型模拟电路的方法，系统和程序产品。

公开(公告)号：US20080093705A1

公开(公告)日：2008-04-24

申请号：US11843777

申请日：2007-08-23

Applicant: Kwang-kyu BANG ,  Jun-ho JANG ,  Yoo-mi LEE

Inventor： Kwang-kyu BANG ,  Jun-ho JANG ,  Yoo-mi LEE

IPC: H01L29/00 ,  H01L21/44

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a fuse structure that can prevent a bridge between a fuse pattern and a guard ring, and a method of fabricating the same are provided. The fuse pattern formed on a multiple-layered metal interconnect layer is stepped shape increasing a vertical distance between the fuse pattern and the guard ring.

Abstract translation: 具有可以防止熔丝图案和保护环之间的桥接的熔丝结构的半导体器件及其制造方法。 形成在多层金属互连层上的熔丝图形是增加熔丝图案和保护环之间的垂直距离的阶梯形状。

公开(公告)号：US20070037078A1

公开(公告)日：2007-02-15

申请号：US11463826

申请日：2006-08-10

Applicant: Kun-Gu LEE ,  Ki-Ho SEONG ,  Yoo-Mi LEE

Inventor： Kun-Gu LEE ,  Ki-Ho SEONG ,  Yoo-Mi LEE

IPC: G03C5/00

CPC classification number: G01R31/318511 ,  G01R31/2831 ,  G01R31/3193

Abstract: A reference wafer for calibrating a laser and a camera and checking laser accuracy and spot size. The reference wafer may include a light absorption layer on a semiconductor substrate and a light reflection layer pattern on the light absorption layer. The light reflection layer pattern may include a first pattern for checking the laser accuracy and spot size and a second pattern for calibrating the laser and camera. A first anti-reflective layer may be introduced between the light absorption layer and the semiconductor substrate, and a second anti-reflective layer may be introduced between the light absorption layer and the light reflection layer pattern.

Abstract translation: 用于校准激光和相机的参考晶片，并检查激光精度和光斑尺寸。 参考晶片可以包括半导体衬底上的光吸收层和光吸收层上的光反射层图案。 光反射层图案可以包括用于检查激光精度和光斑尺寸的第一图案和用于校准激光和照相机的第二图案。 可以在光吸收层和半导体衬底之间引入第一抗反射层，并且可以在光吸收层和光反射层图案之间引入第二抗反射层。

公开(公告)号：US20080116527A1

公开(公告)日：2008-05-22

申请号：US11561537

申请日：2006-11-20

Applicant: Terence B. Hook ,  Jeffrey B. Johnson ,  Yoo-Mi Lee

Inventor： Terence B. Hook ,  Jeffrey B. Johnson ,  Yoo-Mi Lee

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L27/0207

Abstract: Methods of improving operational parameters between at least a pair of matched transistors, and a set of transistors, are disclosed. One embodiment of a method includes a method of improving at least one of a threshold voltage (Vt) mismatch and current drive between at least a pair of matched transistors for analog applications, the method comprising: forming at least a pair of transistors, each with a gate having a plurality of connected fingers; and optimizing a total length of a channel under the plurality of fingers to attain at least one of: a) a reduced threshold voltage mismatch between the at least pair of transistors, and b) increased current drive for a given threshold voltage mismatch, between the at least pair of transistors, each finger having a length less than an overall length of the channel.

Abstract translation: 公开了改善至少一对匹配晶体管之间的操作参数的方法和一组晶体管。 方法的一个实施例包括一种改进用于模拟应用的至少一对匹配晶体管之间的阈值电压（Vt）失配和电流驱动中的至少一个的方法，所述方法包括：形成至少一对晶体管，每个晶体管具有 具有多个连接的手指的门; 以及优化所述多个指状物下的通道的总长度以达到以下至少一个：a）所述至少一对晶体管之间的阈值电压失配降低，以及b）对于给定阈值电压失配的增加的电流驱动， 至少一对晶体管，每个手指的长度小于通道的总长度。

公开(公告)号：US20060100873A1

公开(公告)日：2006-05-11

申请号：US10904307

申请日：2004-11-03

Applicant: Calvin Bittner ,  Steven Grundon ,  Yoo-Mi Lee ,  Ning Lu ,  Josef Watts

Inventor： Calvin Bittner ,  Steven Grundon ,  Yoo-Mi Lee ,  Ning Lu ,  Josef Watts

IPC: G10L15/14

CPC classification number: G06F17/5036

Abstract: A method, system and program product are disclosed for statistical modeling an integrated circuit that provides information about partial correlations between model parameters. The invention determines a variance-covariance matrix for data to be modeled; conducts principal component analysis on the variance-covariance matrix; and creates a statistical model with an independent distribution for each principal component, allowing calculation of each individual model parameter as a weighted sum by a circuit simulator. The statistical model provides information about how well individual transistors will track one another based on layout similarity. This allows the designer to quantify and take advantage of design practices that make all transistors similar, for example, by orienting all gates in the same direction. A method, system and program product for simulating a circuit using the statistical model are also included.

Abstract translation: 公开了一种用于统计建模集成电路的方法，系统和程序产品，其提供关于模型参数之间的部分相关性的信息。 本发明确定要建模的数据的方差 - 协方差矩阵; 对方差协方差矩阵进行主成分分析; 并为每个主成分创建一个具有独立分布的统计模型，允许通过电路模拟器计算每个单独的模型参数作为加权和。 统计模型提供了有关单个晶体管基于布局相似性将彼此跟踪的信息。 这允许设计者量化并利用使所有晶体管相似的设计实践，例如通过将所有栅极定向在相同的方向。 还包括用于使用统计模型模拟电路的方法，系统和程序产品。