公开(公告)号：US09418947B2

公开(公告)日：2016-08-16

申请号：US13406031

申请日：2012-02-27

Applicant: Yu-Feng Chen ,  Chun-Hung Lin ,  Han-Ping Pu ,  Ming-Da Cheng ,  Kai-Chiang Wu

Inventor： Yu-Feng Chen ,  Chun-Hung Lin ,  Han-Ping Pu ,  Ming-Da Cheng ,  Kai-Chiang Wu

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03334 ,  H01L2224/0384 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05075 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1184 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13078 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/206 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements.

Abstract translation: 所描述的形成用于封装封装的连接器的机构的实施例使得具有更细间距的较小连接器能够实现更小的封装尺寸和附加的连接。 一个封装上的导电元件部分地嵌入封装的模制化合物中，以与另一封装上的触点或金属焊盘结合。 通过嵌入导电元件，可以使导电元件更小，并且在导电元件和模塑料之间存在间隙。 可以通过将连接器的最大宽度添加空间余量来确定连接器的间距。 另一个封装上的各种类型的触点可以结合到导电元件上。

公开(公告)号：US20060027918A1

公开(公告)日：2006-02-09

申请号：US10911585

申请日：2004-08-05

Applicant: Kai-Chiang Wu ,  Shaw-Wei Chen

Inventor： Kai-Chiang Wu ,  Shaw-Wei Chen

IPC: H01L23/34

CPC classification number: H01L23/585 ,  H01L24/10 ,  H01L2924/0102 ,  H01L2924/01079 ,  H05K3/0052 ,  H05K3/242 ,  H05K2201/09036 ,  H05K2201/0909

Abstract: An electroplated wire layout for package sawing comprises a substrate with a plurality of chip arrays disposed thereon. A kerf having two scribe lines is disposed between every two chip arrays. Several solder ball pads corresponding to the chip arrays are disposed on a back surface of the substrate. Each solder ball pad has a solder ball electroplated wire extended into a kerf. There is also a kerf electroplated wire disposed in each kerf and above the scribe lines of the kerf in a zigzag way. The kerf electroplated wire is connected with the solder ball pad electroplated wires to achieve electric connection. By changing the shape of the kerf electroplated wire, the kerf electroplated wire can be easily cut off to enhance the yield and reliability and also lower the cost.

Abstract translation: 用于包装锯切的电镀线布局包括其上布置有多个芯片阵列的基板。 在每两个芯片阵列之间设置具有两个划痕线的切口。 对应于芯片阵列的几个焊球垫设置在基板的背面上。 每个焊球垫具有延伸到切口中的焊球电镀丝。 还有一个切口电镀线，以锯齿形的方式设置在每个切口上并且在切口的划线之上。 切割电镀线与焊球电镀线连接，实现电连接。 通过改变切口电镀线的形状，切割电镀线可以容易地切断，以提高产量和可靠性，并降低成本。

公开(公告)号：US06937477B2

公开(公告)日：2005-08-30

申请号：US10760356

申请日：2004-01-21

Applicant: Kai-Chiang Wu

Inventor： Kai-Chiang Wu

IPC: H01L23/49 ,  H01L23/52 ,  H01L25/065 ,  H05K1/11 ,  H05K7/02

CPC classification number: H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/27013 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention provides an improved structure of gold fingers, which is to redesign a conventional gold finger on a packaging substrate into a gold finger set that contains a plurality of gold finger units. Between each single gold finger unit, there exists an electrical connection. Therefore, in the structure of stacked-chip packaging, each wire that is connected through wire bonding on the same gold finger of each layer chip can separately perform wire bonding on different gold finger units of the same gold finger set. Due to the improvement on the gold finger structure, the present invention can prevent the adhesive on a chip from flowing along the wire bonding path of a layer chip and smearing the whole gold finger. Thus, other layer chips can be prevented from being unable to perform wire bonding.

Abstract translation: 本发明提供一种金手指的改进结构，其是将包装衬底上的常规金手指重新设计成包含多个金手指单元的金手指组。 在每个单金指单元之间，存在电连接。 因此，在堆叠式芯片封装的结构中，通过在每层芯片的同一金手指上通过引线键合连接的每根导线可以分别在相同金手指组的不同金手指单元上进行引线接合。 由于金手指结构的改善，本发明可以防止芯片上的粘合剂沿着层芯片的引线接合路径流动并涂抹整个金手指。 因此，可以防止其他层芯片不能进行引线接合。

公开(公告)号：US20050110126A1

公开(公告)日：2005-05-26

申请号：US10720524

申请日：2003-11-25

Applicant: Kai-Chiang Wu

Inventor： Kai-Chiang Wu

IPC: H01L21/58 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L23/02

CPC classification number: H01L24/32 ,  H01L23/3128 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83136 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The claimed invention discloses a chip adhesive that is adhered to a stacked packaging structure between two adjacent chips. The chip adhesive includes a plurality of stuff particles to keep the chip adhesive with a predetermined thickness through suitably controlling type and quantity of the stuff particle. Two adjacent chips can be adhered together with a specific gap. The cost of dummy die can be saved and the space for wiring bonding can be retained. The chips of the stacked packaging structure, moreover, can be packaged with a faced-up type to reduce the cost of applying flip chip type or WBGA type.

Abstract translation: 要求保护的发明公开了一种芯片粘合剂，其粘附到两个相邻芯片之间的堆叠封装结构。 芯片粘合剂包括多个填料颗粒，以通过适当地控制填料颗粒的类型和数量来将芯片粘合剂保持在预定厚度。 两个相邻的芯片可以以特定间隙粘合在一起。 可以节省虚拟模具的成本，并且可以保持用于布线接合的空间。 此外，堆叠式封装结构的芯片可以面朝上封装，以降低应用倒装芯片型或WBGA型的成本。

公开(公告)号：US06633086B1

公开(公告)日：2003-10-14

申请号：US10162910

申请日：2002-06-06

Applicant: Yi-Liang Peng ,  Kai-Chiang Wu

Inventor： Yi-Liang Peng ,  Kai-Chiang Wu

IPC: H01L2348

CPC classification number: H01L25/0657 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention provides a stacked chip scale package structure, wherein a lower chip and an upper chip are stacked on a substrate. Two rows of bonding pads are disposed on each of the upper and lower chips. The bonding pads on the upper and lower chips are parallel arranged. At least a dummy die is disposed below the suspended portion of the upper chip and at the side of the lower chip as a support during wire bonding. A gap is reserved between the dummy die and the lower chip. The present invention utilizes the design of dummy die to resolve the problem of die crack caused by wire bonding of suspended chip. Therefore, the present invention can flexibly adjust the size and installation direction of the upper chip to meet the requirement of substrate layout, and can also shorten the trace length on the substrate to enhance the electric performance thereof.

Abstract translation: 本发明提供一种堆叠式芯片级封装结构，其中下部芯片和上部芯片堆叠在基板上。 两排接合焊盘设置在上和下芯片的每一个上。 上芯片和下芯片上的焊盘平行布置。 在引线接合期间，至少一个虚设裸片设置在上芯片的悬挂部分下方和下芯片的侧面作为支撑。 在虚设管芯和下部芯片之间保留间隙。 本发明利用虚拟模具的设计来解决悬挂芯片引线接合引起的模具裂纹问题。 因此，本发明可以灵活地调节上芯片的尺寸和安装方向，以满足基板布局的要求，并且还可以缩短基板上的走线长度以增强其电气性能。

公开(公告)号：US08703539B2

公开(公告)日：2014-04-22

申请号：US13539182

申请日：2012-06-29

Applicant: Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Jui-Pin Hung ,  Chien-Hsiun Lee ,  Kai-Chiang Wu

Inventor： Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Jui-Pin Hung ,  Chien-Hsiun Lee ,  Kai-Chiang Wu

IPC: H01L21/50

CPC classification number: H01L23/5384 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81424 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81471 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00

Abstract: System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly.

Abstract translation: 用于提供多芯片插入器结构的系统和方法。 一个实施例包括在模制插入器中的多个插入器螺柱，在插入器的每一侧具有重定向层。 此外，插入器支柱可以在模制插入件之前通过焊接或引线焊接来初始地附接到导电安装板，其中蚀刻安装板以形成其中一个重定向层。 集成电路管芯可以附接到插入器的每一侧上的重定向层，以及用于将具有第三集成电路的顶部封装电连接到插入器组件的层间连接结构。

公开(公告)号：US20140001612A1

公开(公告)日：2014-01-02

申请号：US13539182

申请日：2012-06-29

Applicant: Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Jui-Pin Hung ,  Chien-Hsun Lee ,  Kai-Chiang Wu

Inventor： Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Jui-Pin Hung ,  Chien-Hsun Lee ,  Kai-Chiang Wu

IPC: H01L23/495 ,  H01L25/065 ,  H01L21/98

CPC classification number: H01L23/5384 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81424 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81471 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00

Abstract: System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly.

Abstract translation: 用于提供多芯片插入器结构的系统和方法。 一个实施例包括在模制插入器中的多个插入器螺柱，在插入器的每一侧具有重定向层。 此外，插入器支柱可以在模制插入件之前通过焊接或引线焊接来初始地附接到导电安装板，其中蚀刻安装板以形成其中一个重定向层。 集成电路管芯可以附接到插入器的每一侧上的重定向层，以及用于将具有第三集成电路的顶部封装电连接到插入器组件的层间连接结构。

公开(公告)号：US20130292831A1

公开(公告)日：2013-11-07

申请号：US13463667

申请日：2012-05-03

Applicant: Ming-Kai Liu ,  Shih-Wei Liang ,  Hsien-Wei Chen ,  Kai-Chiang Wu

Inventor： Ming-Kai Liu ,  Shih-Wei Liang ,  Hsien-Wei Chen ,  Kai-Chiang Wu

IPC: H01L23/52 ,  H01L23/488 ,  H01L21/50

CPC classification number: H01L24/17 ,  H01L21/50 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/52 ,  H01L24/13 ,  H01L24/15 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17519 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81986 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81805

Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package.

公开(公告)号：US20050156303A1

公开(公告)日：2005-07-21

申请号：US10760356

申请日：2004-01-21

Applicant: Kai-Chiang Wu

Inventor： Kai-Chiang Wu

IPC: H01L23/49 ,  H01L23/52 ,  H01L25/065 ,  H05K1/11 ,  H05K7/02

CPC classification number: H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/27013 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention provides an improved structure of gold fingers, which is to redesign a conventional gold finger on a packaging substrate into a gold finger set that contains a plurality of gold finger units. Between each single gold finger unit, there exists an electrical connection. Therefore, in the structure of stacked-chip packaging, each wire that is connected through wire bonding on the same gold finger of each layer chip can separately perform wire bonding on different gold finger units of the same gold finger set. Due to the improvement on the gold finger structure, the present invention can prevent the adhesive on a chip from flowing along the wire bonding path of a layer chip and smearing the whole gold finger. Thus, other layer chips can be prevented from being unable to perform wire bonding.

Abstract translation: 本发明提供一种金手指的改进结构，其是将包装衬底上的常规金手指重新设计成包含多个金手指单元的金手指组。 在每个单金指单元之间，存在电连接。 因此，在堆叠式芯片封装的结构中，通过在每层芯片的同一金手指上通过引线键合连接的每根导线可以分别在相同金手指组的不同金手指单元上进行引线接合。 由于金手指结构的改善，本发明可以防止芯片上的粘合剂沿着层芯片的引线接合路径流动并涂抹整个金手指。 因此，可以防止其他层芯片不能进行引线接合。

公开(公告)号：US06570263B1

公开(公告)日：2003-05-27

申请号：US10162912

申请日：2002-06-06

Applicant: Kai-Chiang Wu ,  Yi-Liang Peng ,  Ya-Yun Cheng

Inventor： Kai-Chiang Wu ,  Yi-Liang Peng ,  Ya-Yun Cheng

IPC: H01L23544

CPC classification number: H05K3/242 ,  H01L23/544 ,  H01L23/585 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2924/0002 ,  H05K1/0269 ,  H05K3/0052 ,  H05K3/28 ,  H05K2201/09781 ,  H05K2201/09918 ,  H01L2924/00

Abstract: The present invention provides a design structure of an plated wire of a fiducial mark for a die-dicing package. In the present structure, a cutting line is positioned between each two adjacent ball grid array (BGA) chips. There is configured a solder mask opening at the edge connecting region of the cutting lines. A fiducial mark is positioned in the opening of each BGA chip, wherein the fiducial mark is close to the cutting line and positioned a plated wire therein to pull from the fiducial mark to out the opening and to connect to the plated wire of the cutting line. So as all the plated wires utilizing the coverage of the solder mask can be entirely cut without the pulling problem from the cutter. The present invention provides a new design structure of the plated wire to overcome the burr effect of prior die dicing so as to enhance the product efficiency and decrease the manufacturing cost.

Abstract translation: 本发明提供了用于芯片划片封装的基准标记的电镀线的设计结构。 在本结构中，切割线位于每个两个相邻的球栅阵列（BGA）芯片之间。 在切割线的边缘连接区域处设置有焊接掩模开口。 每个BGA芯片的开口中都有一个基准标记，其中基准标记靠近切割线，并将电镀线放置在其中以从基准标记拉出开口，并连接到切割线的电镀线 。 因此，利用焊接掩模的覆盖的所有电镀线可以完全切割而不会从切割器引起问题。 本发明提供了一种电镀线的新设计结构，以克服现有的芯片切割的毛刺效应，从而提高产品效率并降低制造成本。