公开(公告)号：US08576100B2

公开(公告)日：2013-11-05

申请号：US13182660

申请日：2011-07-14

申请人： Paul Daniel Imthurn ,  Wei Cheng Joseph Ku

发明人： Paul Daniel Imthurn ,  Wei Cheng Joseph Ku

IPC分类号： H03M7/00

CPC分类号： H03M7/30 ,  H03M7/40 ,  H03M7/4006 ,  H04N19/436 ,  H04N19/46 ,  H04N19/91

摘要： An entropy encoder block for use in a context adaptive encoder and an entropy decoder block for use in a context adaptive decoder is presented. The encoder block includes a plurality of encoding elements, for processing encoding search tree look tables corresponding to encoding probabilities used by the context adaptive encoder, at least two of the encoding elements servicing the same probability. In an embodiment, at least one of the encoding search tree lookup tables comprises a set of shared encoding search tree lookup tables, accessible by at least two of the encoding elements. The decoder block includes a plurality of decoding elements, for processing decoding search tree lookup tables corresponding to the decoding probabilities used by the context adaptive decoder, at least two of the decoding elements servicing the same probability. In an embodiment, at least one of the decoding search tree lookup tables comprises a set of shared decoding search tree lookup tables, accessible by at least two of the decoding elements.

摘要翻译： 提出了一种在上下文自适应编码器中使用的熵编码器块和用于上下文自适应解码器的熵解码器块。 编码器块包括多个编码元件，用于处理与上下文自适应编码器使用的编码概率相对应的编码搜索树查看表，至少两个编码元件服务于相同概率。 在一个实施例中，编码搜索树查找表中的至少一个包括一组可由至少两个编码元素访问的共享编码搜索树查找表。 解码器块包括多个解码元件，用于处理与上下文自适应解码器使用的解码概率相对应的解码搜索树查找表，服务于相同概率的解码元素中的至少两个。 在一个实施例中，解码搜索树查找表中的至少一个包括可由至少两个解码元素访问的一组共享解码搜索树查找表。

公开(公告)号：US08416104B2

公开(公告)日：2013-04-09

申请号：US13092698

申请日：2011-04-22

申请人： Weicheng Joseph Ku ,  Paul Daniel Imthurn

发明人： Weicheng Joseph Ku ,  Paul Daniel Imthurn

IPC分类号： H03M7/40

CPC分类号： H03M7/40 ,  H04N19/436 ,  H04N19/61 ,  H04N19/91

摘要： An entropy decoder and method for decoding code words with an indication of associated probability for each code word. The decoder may include an input buffer in communication with a branch node block, the branch node block in communication with a leaf node block. The input buffer operable to receive code words and the indication of associated probability. The branch node block comprising one or more branch node lookup tables and branch node control logic. The branch node control logic operable to process a code word in the input buffer using a selected table from the one or more branch node lookup tables to obtain leaf node information and a bit count of a code word size, the branch control logic further operable to refresh the input buffer to replace the bit count of the code word size and to make the leaf node information and the table selection available to the leaf node block. The leaf node block may include one or more leaf node lookup tables and leaf node control logic. The leaf node control logic operable to process the leaf node information and the table selection made available by the branch node block to obtain leaf node contents.

摘要翻译： 一种熵解码器和方法，用于对每个代码字具有相关联概率的指示来对码字进行解码。 解码器可以包括与分支节点块通信的输入缓冲器，分支节点块与叶节点块通信。 输入缓冲器可操作以接收代码字和相关概率的指示。 分支节点块包括一个或多个分支节点查找表和分支节点控制逻辑。 所述分支节点控制逻辑可操作以使用来自所述一个或多个分支节点查找表的所选择的表来处理所述输入缓冲器中的码字，以获得叶节点信息和码字大小的位计数，所述分支控制逻辑还可操作为 刷新输入缓冲区以替换代码字大小的位计数，并使叶节点信息和表选择可用于叶节点块。 叶节点块可以包括一个或多个叶节点查找表和叶节点控制逻辑。 叶节点控制逻辑可操作以处理叶节点信息和由分支节点块可用的表选择以获得叶节点内容。

公开(公告)号：US20120102334A1

公开(公告)日：2012-04-26

申请号：US13131019

申请日：2009-11-24

申请人： Daniel O'Loughlin ,  Keelan Smith ,  Jay Scott Fuller ,  Joseph Ku ,  William Lattin ,  Marinus Struik ,  Yuri Poeluev ,  Martthew J. Campagna ,  Thomas Stiemerling

发明人： Daniel O'Loughlin ,  Keelan Smith ,  Jay Scott Fuller ,  Joseph Ku ,  William Lattin ,  Marinus Struik ,  Yuri Poeluev ,  Martthew J. Campagna ,  Thomas Stiemerling

IPC分类号： G06F12/14

CPC分类号： G06F12/1408 ,  G06F21/123 ,  G06F21/57 ,  G06F21/606 ,  G06F21/72 ,  G06F21/73 ,  G06F21/76 ,  G06F21/80 ,  G06F2212/1052 ,  G06F2221/2101 ,  H04L9/0877 ,  H04L9/3066 ,  H04L9/3252 ,  H04L9/3263 ,  H04L9/3273 ,  H04L2209/24

摘要： An asset management system is provided, which includes a hardware module operating as an asset control core. The asset control core generally includes a small hardware core embedded in a target system on chip that establishes a hardware-based point of trust on the silicon die. The asset control core can be used as a root of trust on a consumer device by having features that make it difficult to tamper with. The asset control core is able to generate a unique identifier for one device and participate in the tracking and provisioning of the device through a secure communication channel with an appliance. The appliance generally includes a secure module that caches and distributes provisioning data to one of many agents that connect to the asset control core, e.g. on a manufacturing line or in an after-market programming session.

摘要翻译： 提供资产管理系统，其中包括作为资产控制核心运行的硬件模块。 资产控制核心通常包括嵌入在目标片上系统中的小型硬件核心，其在硅芯片上建立基于硬件的信任点。 资产控制核心可以作为消费者设备的信任根源，具有使其难以篡改的特征。 资产控制核心能够为一个设备生成唯一的标识符，并通过与设备的安全通信通道参与设备的跟踪和配置。 该设备通常包括一个安全模块，它将配置数据高速缓存并分配给连接到资产控制核心的许多代理之一，例如， 在生产线上或在售后市场的程序设计会议。

公开(公告)号：US20120022861A1

公开(公告)日：2012-01-26

申请号：US13182660

申请日：2011-07-14

申请人： Paul Daniel Imthurn ,  Wei Cheng Joseph Ku

发明人： Paul Daniel Imthurn ,  Wei Cheng Joseph Ku

IPC分类号： G10L19/02

CPC分类号： H03M7/30 ,  H03M7/40 ,  H03M7/4006 ,  H04N19/436 ,  H04N19/46 ,  H04N19/91

摘要： An entropy encoder block for use in a context adaptive encoder and an entropy decoder block for use in a context adaptive decoder is presented. The encoder block includes a plurality of encoding elements, for processing encoding search tree look tables corresponding to encoding probabilities used by the context adaptive encoder, at least two of the encoding elements servicing the same probability. In an embodiment, at least one of the encoding search tree lookup tables comprises a set of shared encoding search tree lookup tables, accessible by at least two of the encoding elements. The decoder block includes a plurality of decoding elements, for processing decoding search tree lookup tables corresponding to the decoding probabilities used by the context adaptive decoder, at least two of the decoding elements servicing the same probability. In an embodiment, at least one of the decoding search tree lookup tables comprises a set of shared decoding search tree lookup tables, accessible by at least two of the decoding elements.

摘要翻译： 提出了一种在上下文自适应编码器中使用的熵编码器块和用于上下文自适应解码器的熵解码器块。 编码器块包括多个编码元件，用于处理与上下文自适应编码器使用的编码概率相对应的编码搜索树查看表，至少两个编码元件服务于相同概率。 在一个实施例中，编码搜索树查找表中的至少一个包括一组可由至少两个编码元素访问的共享编码搜索树查找表。 解码器块包括多个解码元件，用于处理与上下文自适应解码器使用的解码概率相对应的解码搜索树查找表，服务于相同概率的解码元素中的至少两个。 在一个实施例中，解码搜索树查找表中的至少一个包括可由至少两个解码元素访问的一组共享解码搜索树查找表。

公开(公告)号：US06492854B1

公开(公告)日：2002-12-10

申请号：US09941581

申请日：2001-08-30

申请人： Joseph Ku ,  Stuart Siu

发明人： Joseph Ku ,  Stuart Siu

IPC分类号： H03K3286

CPC分类号： H03K3/037 ,  H03K3/012

摘要： A power efficient flip-flop includes a power switch regulating power supplied to a high speed latch in the flip-flop. When the power switch is activated, causing the high speed latch to receive power, the high speed latch captures data received by the flip-flop. The captured data is propagated by the high speed latch to the output of the flip-flop. Simultaneously, the high speed latch transmits the data to a low leakage latch connected to the high speed latch. Then, power is removed from the high speed latch, and the data retained in the low leakage static latch is now released to the output of the flip-flop. The power efficient flip-flop minimizes leakage current generated by the high speed latch by removing a path to ground when power is not provided to the high speed latch. A decoupling device is connected to the power switch to substantially eliminate a coupling effect.

摘要翻译： 功率高效触发器包括调节提供给触发器中的高速锁存器的功率的电源开关。 当电源开关被激活时，导致高速锁存器接收电力，高速锁存器捕获由触发器接收到的数据。 捕获的数据由高速锁存器传播到触发器的输出。 同时，高速锁存器将数据发送到连接到高速锁存器的低泄漏锁存器。 然后，从高速锁存器中移除电源，并且保留在低泄漏静态锁存器中的数据现在释放到触发器的输出。 功率高效触发器通过在没有向高速锁存器提供电力时去除对地的路径来最小化由高速锁存器产生的漏电流。 解耦装置连接到电源开关以基本上消除耦​​合效应。

公开(公告)号：US5874342A

公开(公告)日：1999-02-23

申请号：US890222

申请日：1997-07-09

申请人： Jiunn-Yann Tsai ,  Zhihai Wang ,  Yen-Hui Joseph Ku

发明人： Jiunn-Yann Tsai ,  Zhihai Wang ,  Yen-Hui Joseph Ku

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L21/336

CPC分类号： H01L29/66575 ,  H01L21/2257 ,  H01L29/665

摘要： A process which is capable of forming shallow source/drain regions in a silicon substrate and a doped gate electrode by implantation of cobalt silicide contacts of uniform thickness previously formed on the substrate followed by diffusion of the dopant into the substrate to form the desired source/drain regions, and into the polysilicon gate electrode to provide the desired conductivity is described. The process comprises: first depositing a layer of cobalt over a polysilicon gate electrode and areas of a silicon substrate where source/drain regions will be formed; then forming at least one capping layer over the cobalt layer; then annealing the structure at a first temperature to form cobalt silicide; then removing the capping layer, as well as the unreacted cobalt and any cobalt reaction products other than cobalt silicide; then annealing the structure again at a higher temperature than the first anneal to form high temperature cobalt silicide; then implanting the cobalt silicide with one or more dopants suitable for forming source/drain regions in the silicon substrate and for increasing the conductivity of the polysilicon gate electrode; and then heating the structure sufficiently to cause the implanted dopant or dopants in the cobalt silicide to diffuse into the substrate to form the desired source/drain regions and into the polysilicon gate electrode to increase the conductivity thereof.

摘要翻译： 能够通过在衬底上注入预先形成均匀厚度的钴硅化物触点，然后将掺杂剂扩散到衬底中以形成所需的源极/漏极区域，从而在硅衬底和掺杂栅电极中形成浅源极/漏极区域的工艺， 漏极区域和多晶硅栅电极以提供期望的导电性。 该方法包括：首先在多晶硅栅极上沉积一层钴，并在其上形成源极/漏极区的硅衬底区域; 然后在所述钴层上形成至少一个覆盖层; 然后在第一温度下退火该结构以形成硅化钴; 然后除去覆盖层，以及未反应的钴和除了硅化钴之外的任何钴反应产物; 然后在比第一退火更高的温度下再次退火结构以形成高温钴硅酸盐; 然后用适合于在硅衬底中形成源/漏区的一种或多种掺杂剂注入硅化钴，并增加多晶硅栅电极的导电性; 然后充分加热该结构，使得硅化钴中的注入的掺杂剂或掺杂剂扩散到衬底中以形成所需的源极/漏极区并进入多晶硅栅电极以增加其导电性。

公开(公告)号：US07248518B2

公开(公告)日：2007-07-24

申请号：US11129269

申请日：2005-05-12

申请人： Joseph Ku ,  James Robert Eaton

发明人： Joseph Ku ,  James Robert Eaton

IPC分类号： G11C7/00

CPC分类号： G11C8/10 ,  G11C7/12 ,  G11C7/22 ,  G11C17/06

摘要： The invention includes an apparatus and method of selecting memory cells within a memory array. The method includes receiving a memory cell address. A column address and a row address are generated from the memory cell address. Row select lines or column select lines are pre-charged. A self-timed charging circuit is initiated to provide an adequate amount of time to charge a selected row, and to initiate elimination of static current flowing to unselected rows after a self-timed delay. The other of the row select lines or the column select lines are then pre-charged. Memory cells are selected based upon the column address and the row address. One of two states of the memory cells can be based upon sensing threshold voltages of sense lines that correspond with the selected memory cells.

摘要翻译： 本发明包括一种选择存储器阵列内的存储单元的装置和方法。 该方法包括接收存储单元地址。 从存储单元地址生成列地址和行地址。 行选择行或列选择行已预充电。 启动自定时充电电路以提供足够的时间来对所选择的行进行充电，并且在自定时延迟之后开始消除流向未选择的行的静态电流。 然后，其他行选择行或列选择行将被预充电。 基于列地址和行地址选择存储单元。 存储器单元的两种状态之一可以基于感测线对应于所选存储单元的阈值电压。

公开(公告)号：US20050246558A1

公开(公告)日：2005-11-03

申请号：US10836018

申请日：2004-04-29

申请人： Joseph Ku

发明人： Joseph Ku

IPC分类号： G06F1/20 ,  G06F1/26

CPC分类号： G06F1/206 ,  Y02D10/16

摘要： A computer system includes a memory module. Power management in the computer system is performed with at least one temperature rise parameter (ΔTx) of the memory module.

摘要翻译： 计算机系统包括存储器模块。 使用存储器模块的至少一个温度上升参数（DeltaTx）执行计算机系统中的电源管理。

公开(公告)号：US20050232023A1

公开(公告)日：2005-10-20

申请号：US11129269

申请日：2005-05-12

申请人： Joseph Ku ,  James Eaton

发明人： Joseph Ku ,  James Eaton

IPC分类号： G11C17/18 ,  G11C5/00 ,  G11C5/06 ,  G11C7/00 ,  G11C7/12 ,  G11C7/22 ,  G11C8/10 ,  G11C17/06

CPC分类号： G11C8/10 ,  G11C7/12 ,  G11C7/22 ,  G11C17/06

摘要： The invention includes an apparatus and method of selecting memory cells within a memory array. The method includes receiving a memory cell address. A column address and a row address are generated from the memory cell address. Row select lines or column select lines are pre-charged. A self-timed charging circuit is initiated to provide an adequate amount of time to charge a selected row, and to initiate elimination of static current flowing to unselected rows after a self-timed delay. The other of the row select lines or the column select lines are then pre-charged. Memory cells are selected based upon the column address and the row address. One of two states of the memory cells can be based upon sensing threshold voltages of sense lines that correspond with the selected memory cells.

摘要翻译： 本发明包括一种选择存储器阵列内的存储单元的装置和方法。 该方法包括接收存储单元地址。 从存储单元地址生成列地址和行地址。 行选择行或列选择行已预充电。 启动自定时充电电路以提供足够的时间来对所选择的行进行充电，并且在自定时延迟之后开始消除流向未选择的行的静态电流。 然后，其他行选择行或列选择行将被预充电。 基于列地址和行地址选择存储单元。 存储器单元的两种状态之一可以基于感测线对应于所选存储单元的阈值电压。

公开(公告)号：US06907534B2

公开(公告)日：2005-06-14

申请号：US09894142

申请日：2001-06-29

申请人： Joseph Ku

发明人： Joseph Ku

IPC分类号： G06F1/32 ,  G06F9/38 ,  G06F1/26 ,  H03K17/23

CPC分类号： G06F1/3203 ,  G06F9/3869

摘要： Power consumption in a circuit is minimized. The circuit includes a pipelined circuit having a plurality of stages. A determination is made as to whether a predetermined period of time has expired. The predetermined period of time being associated with a predetermined period of time to detect a transition of an input or an output of the pipelined circuit. If the predetermined period of time is exceeded, a sequential shut-down procedure is performed on each stage in the plurality of stages of the pipelined circuit so that each stage is shut-down.

摘要翻译： 电路中的功耗最小化。 该电路包括具有多个级的流水线电路。 确定预定时间段是否已经过期。 预定时间段与预定时间段相关联，以检测流水线电路的输入或输出的转变。 如果超过预定时间段，则在流水线电路的多个级中的每个级上执行顺序关闭过程，以使每个级被关闭。