公开(公告)号：US06492854B1

公开(公告)日：2002-12-10

申请号：US09941581

申请日：2001-08-30

申请人： Joseph Ku ,  Stuart Siu

发明人： Joseph Ku ,  Stuart Siu

IPC分类号： H03K3286

CPC分类号： H03K3/037 ,  H03K3/012

摘要： A power efficient flip-flop includes a power switch regulating power supplied to a high speed latch in the flip-flop. When the power switch is activated, causing the high speed latch to receive power, the high speed latch captures data received by the flip-flop. The captured data is propagated by the high speed latch to the output of the flip-flop. Simultaneously, the high speed latch transmits the data to a low leakage latch connected to the high speed latch. Then, power is removed from the high speed latch, and the data retained in the low leakage static latch is now released to the output of the flip-flop. The power efficient flip-flop minimizes leakage current generated by the high speed latch by removing a path to ground when power is not provided to the high speed latch. A decoupling device is connected to the power switch to substantially eliminate a coupling effect.

摘要翻译： 功率高效触发器包括调节提供给触发器中的高速锁存器的功率的电源开关。 当电源开关被激活时，导致高速锁存器接收电力，高速锁存器捕获由触发器接收到的数据。 捕获的数据由高速锁存器传播到触发器的输出。 同时，高速锁存器将数据发送到连接到高速锁存器的低泄漏锁存器。 然后，从高速锁存器中移除电源，并且保留在低泄漏静态锁存器中的数据现在释放到触发器的输出。 功率高效触发器通过在没有向高速锁存器提供电力时去除对地的路径来最小化由高速锁存器产生的漏电流。 解耦装置连接到电源开关以基本上消除耦​​合效应。

公开(公告)号：US06417710B1

公开(公告)日：2002-07-09

申请号：US09698823

申请日：2000-10-26

申请人： William Bartholet

发明人： William Bartholet

IPC分类号： H03K3286

CPC分类号： H03K3/0375

摘要： A single event upset (SEU) hardened latch circuit utilizing two cross-coupled inverters in which the voter output circuitry is fed back to the output node of the latch circuit.

摘要翻译： 使用两个交叉耦合的反相器的单个事件镦粗（SEU）硬化锁存电路，其中选通输出电路被反馈到锁存电路的输出节点。

公开(公告)号：US06404254B2

公开(公告)日：2002-06-11

申请号：US09166585

申请日：1998-10-06

申请人： Hiroaki Iwaki ,  Kouichi Kumagai ,  Susumu Kurosawa

发明人： Hiroaki Iwaki ,  Kouichi Kumagai ,  Susumu Kurosawa

IPC分类号： H03K3286

CPC分类号： H03K3/356156 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356173

摘要： A semiconductor integrated circuit so configured to stop the supplying of an electric power to a logic circuit in a standby mode, thereby to realize a low power consumption, includes a latch circuit characterized in that as the control signal a clock signal is supplied in the active mode, and a signal for creating an information hold condition is supplied in the standby mode, and in that MOSFETs applied with a control signal include a first conductivity type MOSFET having a high threshold and a second conductivity type MOSFET having a low threshold, a voltage amplitude of the control signal being larger than a power supply voltage. The semiconductor integrated circuit can be realized in that the high speed operation in the active mode and the low power consumption in the standby mode are compatible with each other, and it is sufficient if a power switch for the logic circuit is inserted at only either of the high level power supply voltage line side and the low level power supply voltage line side. In addition, the control signals are very few, and a fine timing control for changing over the mode is no longer required.

摘要翻译： 一种半导体集成电路，其被配置为在备用模式中停止向逻辑电路供电，从而实现低功耗，包括锁存电路，其特征在于，作为控制信号，时钟信号在主动 模式，并且在备用模式下提供用于创建信息保持条件的信号，并且施加控制信号的MOSFET包括具有高阈值的第一导电型MOSFET和具有低阈值的第二导电类型MOSFET， 控制信号的幅度大于电源电压。 可以实现半导体集成电路，即主动模式中的高速操作和待机模式中的低功耗彼此兼容，并且如果用于逻辑电路的电源开关仅插入到 高电平电源电压侧和低电平电源电压线一侧。 此外，控制信号非常少，并且不再需要用于改变模式的精细定时控制。

公开(公告)号：US06359485B1

公开(公告)日：2002-03-19

申请号：US09614084

申请日：2000-07-11

申请人： Oleg Drapkin ,  Grigori Temkine

发明人： Oleg Drapkin ,  Grigori Temkine

IPC分类号： H03K3286

CPC分类号： H03K3/0377

摘要： An integrated circuit and method utilizes a differential input receiver having a first input that receives an input signal. A reference voltage adjustment circuit produces a variable reference signal for the second input of a differential input receiver. A feedback path is provided from the output of the differential input receiver to an input of the reference voltage adjustment circuit. The reference voltage adjustment circuit dynamically varies the variable reference voltage signal to facilitate hysteresis. The variable reference voltage signal is lowered in the case of a high input signal, and raised in the case of a low input signal.

摘要翻译： 集成电路和方法利用具有接收输入信号的第一输入的差分输入接收器。 参考电压调节电路产生用于差分输入接收器的第二输入的可变参考信号。 反馈路径从差分输入接收器的输出提供给参考电压调节电路的输入端。 参考电压调节电路动态​​地改变可变参考电压信号以便于滞后。 在高输入信号的情况下，可变参考电压信号降低，并且在低输入信号的情况下升高。

公开(公告)号：US06535042B1

公开(公告)日：2003-03-18

申请号：US09510181

申请日：2000-02-22

申请人： Karl Edwards

发明人： Karl Edwards

IPC分类号： H03K3286

CPC分类号： H03K3/012 ,  H03K3/2825 ,  H03K3/288

摘要： A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

摘要翻译： 提供高速，电流驱动的锁存器。 锁存器传导电流并包括输出，SET电路和RESET电路。 输出在第一状态和第二状态之间变化。 SET电路在第一状态下导通锁存器中存在的电流，使得SET电路保持接近将晶体管的输出从第一电平改变到第二电平所需的电平，并且RESET电路在 第二电平使得RESET电路接近将晶体管的输出从第二电平改变到第一电平所需的电平。

公开(公告)号：US06225846B1

公开(公告)日：2001-05-01

申请号：US08867854

申请日：1997-06-03

申请人： Yoshiki Wada ,  Kimio Ueda

发明人： Yoshiki Wada ,  Kimio Ueda

IPC分类号： H03K3286

CPC分类号： H03K19/01707 ,  H03K19/0027 ,  H03K2217/0018

摘要： A body voltage controlled semiconductor integrated circuit which can solve a problem of a conventional CMOS inverter in that it cannot operate at a supply voltage beyond the built-in voltage of the CMOS transistors if their body electrodes are each connected to their own gate electrodes rather than to their source electrodes to quicken the operation of the CMOS inverter. A voltage divider circuit is provided which conducts during the operation of the CMOS transistors of the inverter so that the body voltages of the PMOS transistor or the NMOS transistor of the inverter is varied in the direction of reducing their threshold voltages. By controlling the size of electrodes and the voltages applied to the body electrodes of transistors constituting the voltage divider circuit, it becomes possible to operate the CMOS inverter at the supply voltage beyond the built-in voltage.

摘要翻译： 一种体电压控制的半导体集成电路，其可以解决常规CMOS反相器的问题，因为如果它们的主体电极各自连接到它们自己的栅电极而不能在超过CMOS晶体管的内置电压的电源电压下工作，而不是 到源极，加快CMOS反相器的工作。 提供了一种分压器电路，其在逆变器的CMOS晶体管的操作期间导通，使得反相器的PMOS晶体管或NMOS晶体管的体电压在减小其阈值电压的方向上变化。 通过控制电极的尺寸和施加到构成分压器电路的晶体管的体电极的电压，可以以超过内置电压的电源电压来操作CMOS反相器。

公开(公告)号：US06208187B1

公开(公告)日：2001-03-27

申请号：US09326358

申请日：1999-06-04

申请人： Michael J. Callahan, Jr.

发明人： Michael J. Callahan, Jr.

IPC分类号： H03K3286

CPC分类号： H03K3/02337 ,  H03K5/2481 ,  H03K5/249

摘要： A high-gain comparator has a built-in hysteresis offset voltage generation feature. The comparator is characterized as having several elements, including a differential amplifier pair that is provided with first and second input voltages, an offset voltage element that creates an offset voltage between the first and second elements of the differential amplifier pair, an output generation element operably coupled to the differential amplifier pair that generates an output voltage of the comparator which is indicative of a voltage difference between the first and second input voltages, and a control element operably coupled to the output signal that controllably adjusts the offset voltage from a first state to a second state in accordance with the output signal to create a hysteresis condition of the comparator.

摘要翻译： 高增益比较器具有内置的滞后偏移电压产生功能。 比较器的特征在于具有若干元件，包括设置有第一和第二输入电压的差分放大器对，在差分放大器对的第一和第二元件之间产生偏移电压的偏移电压元件，可操作地输出的输出产生元件 耦合到所述差分放大器对，所述差分放大器对产生指示所述第一和第二输入电压之间的电压差的所述比较器的输出电压，以及可操作地耦合到所述输出信号的控制元件，所述控制元件可控地将所述偏移电压从第一状态调整到 根据输出信号的第二状态来产生比较器的滞后条件。