公开(公告)号：US08570067B2

公开(公告)日：2013-10-29

申请号：US11749002

申请日：2007-05-15

申请人： Oleg Drapkin ,  Grigori Temkine ,  Marcus Ng ,  Kevin Yikai Liang ,  Arvind Bomdica ,  Siji Menokki Kandiyil ,  Ming So ,  Samu Suryanarayana

发明人： Oleg Drapkin ,  Grigori Temkine ,  Marcus Ng ,  Kevin Yikai Liang ,  Arvind Bomdica ,  Siji Menokki Kandiyil ,  Ming So ,  Samu Suryanarayana

IPC分类号： H03K19/0175

CPC分类号： H03K19/00384 ,  H03K17/223 ,  H04L25/028

摘要： An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.

摘要翻译： 集成电路能够通过使用功率斜坡控制的通信缓冲器逻辑来控制通信信号，以基于电压源上的检测到的电压来产生输出通信信号。 为电源斜坡控制的通信缓冲逻辑电源供电需要电压源。 可以使用功率斜坡传感器逻辑检测电压源上的电压。 如果检测到的电压大于或等于预定电压电平，则输出通信信号基于核心逻辑输出信号。 如果检测到的电压小于预定电压电平，则将输出通信信号预定为三态输出通信信号，逻辑1输出通信信号和逻辑零输出通信信号之一。 功率斜坡控制通信缓冲器逻辑还可以响应于检测到的电压而基于输入通信信号生成核心逻辑输入信号。

公开(公告)号：US20080157817A1

公开(公告)日：2008-07-03

申请号：US12046887

申请日：2008-03-12

申请人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

发明人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

IPC分类号： H03K19/0185

CPC分类号： H03K19/0185 ,  H03K19/094

摘要： An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.

摘要翻译： 输入信号被路由到第一逻辑一个参考信号发生器，或者基于输入信号的至少一个电压电平路由到第二逻辑1参考信号发生器。 当输入信号的电压电平小于阈值时，第一逻辑1参考信号发生器选择性地产生第一逻辑1参考信号。 当输入信号的电压电平大于或等于阈值时，第二逻辑1参考信号发生器交替产生第二逻辑1参考信号。 第一和第二逻辑一个参考信号可以用于控制驱动具有对应于第一逻辑1参考信号的电压电平的逻辑1值的定标输出信号的第一电压缩放电路。

公开(公告)号：US20060038620A1

公开(公告)日：2006-02-23

申请号：US10924145

申请日：2004-08-23

申请人： Oleg Drapkin ,  Grigori Temkine ,  Mikhail Rodionov ,  Michael Foxcroft

发明人： Oleg Drapkin ,  Grigori Temkine ,  Mikhail Rodionov ,  Michael Foxcroft

IPC分类号： H03L7/00

CPC分类号： H03L7/093 ,  H03L7/0891 ,  H03L7/18

摘要： A circuit includes a phase lock loop circuit and a continuous phase lock loop calibration circuit. The continuous phase lock loop calibration circuit is operatively coupled to the PLL circuit and produces a continuous calibration signal based on a reference voltage from a reference voltage circuit to calibrate the PLL circuit on a continuous basis.

摘要翻译： 电路包括锁相环电路和连续锁相环校准电路。 连续锁相环校准电路可操作地耦合到PLL电路，并且基于来自参考电压电路的参考电压产生连续校准信号，以连续地校准PLL电路。

公开(公告)号：US06918047B1

公开(公告)日：2005-07-12

申请号：US09657255

申请日：2000-09-07

申请人： Richard K. Sita ,  Carl Mizuyabu ,  Oleg Drapkin

发明人： Richard K. Sita ,  Carl Mizuyabu ,  Oleg Drapkin

IPC分类号： G06F1/10 ,  G06F1/12 ,  G06F13/00 ,  G11C7/10 ,  H03L7/081 ,  H04L7/04

CPC分类号： G11C7/222 ,  G06F1/10 ,  G06F1/12 ,  G11C7/1072 ,  H03L7/0812 ,  H04L7/0037

摘要： A reference signal input of a delay locked loop is connected to receive a reference clock. The delay locked loop provides a drive clock that drives a clock distribution tree. One of the endpoints of the clock distribution tree is connected to a feedback reference of the delay locked loop. By using one the endpoints as a feedback loop to the delay locked loop the signal received at components attached to the endpoints of the distribution tree can be synchronized to the reference input received at the delay locked loop.

摘要翻译： 连接延迟锁定环路的参考信号输入以接收参考时钟。 延迟锁定环路提供驱动时钟分配树的驱动器时钟。 时钟分配树的端点之一连接到延迟锁定环路的反馈参考。 通过使用一个端点作为延迟锁定环路的反馈回路，在分配树的端点附近的组件处接收到的信号可以被同步到在延迟锁定环路处接收到的参考输入。

公开(公告)号：US06373282B1

公开(公告)日：2002-04-16

申请号：US09379197

申请日：1999-08-20

申请人： Oleg Drapkin ,  Grigori Tempkine

发明人： Oleg Drapkin ,  Grigori Tempkine

IPC分类号： H03K19094

CPC分类号： H03K19/018507 ,  H03K19/00315

摘要： A cascaded output buffer stage and buffering method converts a voltage level of a received internal signal, such as a signal to be output (transmitted) from the cascaded output buffer stage, prior to outputting the received signal; selectively provides a variable reference voltage signal for a cascaded circuit element in the output buffer and also generates a floating well output signal for wells associated the cascaded upper buffer circuit elements. The cascaded output buffer stage is also, in one embodiment, a single gate oxide cascaded output buffer stage. In one embodiment, a voltage level shifting circuit is used along with a variable reference generating circuit that provides a variable reference voltage signal to cascaded output buffer circuits, and that also provides a floating well output signal to wells of the cascaded circuit. The voltage level shifting circuit and variable reference generating circuit is operatively coupled to a cascaded pull up circuit or cascaded pull down circuit as needed.

摘要翻译： 级联输出缓冲级和缓冲方法在输出接收到的信号之前，将所接收的内部信号的电压电平，例如要从级联输出缓冲级输出（发送）的信号转换; 选择性地为输出缓冲器中的级联电路元件提供可变参考电压信号，并且还产生用于与级联的上缓冲电路元件相关联的阱的浮置阱输出信号。 在一个实施例中，级联输出缓冲器级也是单栅极氧化级联输出缓冲级。 在一个实施例中，电压电平移位电路与可变参考产生电路一起使用，该可变参考产生电路向级联输出缓冲器电路提供可变参考电压信号，并且还向级联电路的阱提供浮置阱输出信号。 电压电平移动电路和可变参考产生电路根据需要可操作地耦合到级联上拉电路或级联下拉电路。

公开(公告)号：US06268744B1

公开(公告)日：2001-07-31

申请号：US09609022

申请日：2000-06-30

申请人： Oleg Drapkin ,  Grigori Temkine

发明人： Oleg Drapkin ,  Grigori Temkine

IPC分类号： H03K190185

CPC分类号： H03K19/00315 ,  H03K19/018585

摘要： A buffer circuit utilizes a single gate oxide pre-buffer voltage level shifting circuit on, for example, an output buffer of an I/O pad, to accommodate different I/O pad supply voltages while maintaining normal operating voltages (degradation levels) across boundaries of single gate oxide devices that form the buffer. The single gate oxide output buffer can operate at several different supply voltages. A pre-buffer voltage level shifting circuit includes a multi-supply voltage level shifting circuit having signal gate oxide devices coupled to produce a pre-buffer output signal to an output buffer. A single gate oxide cross coupled active load is coupled to the multi-supply voltage level shifting circuit and provides suitable drive voltages to at least one of cascaded buffer transistors.

摘要翻译： 缓冲电路在例如I / O焊盘的输出缓冲器上使用单栅极氧化物预缓冲器电压电平移位电路，以适应不同的I / O焊盘电源电压，同时保持跨越边界的正常工作电压（劣化电平） 的形成缓冲器的单栅极氧化物器件。 单栅极氧化物输出缓冲器可以在几种不同的电源电压下工作。 预缓冲器电压电平移位电路包括多电源电压移位电路，其具有被耦合以产生到缓冲器输出缓冲器的预缓冲器输出信号的信号栅极氧化器件。 单栅极氧化物交叉耦合有源负载耦合到多电源电压电平移位电路，并向级联缓冲晶体管中的至少一个提供合适的驱动电压。

公开(公告)号：US6160430A

公开(公告)日：2000-12-12

申请号：US274456

申请日：1999-03-22

申请人： Oleg Drapkin ,  Grigori Temkine

发明人： Oleg Drapkin ,  Grigori Temkine

IPC分类号： H03K19/003 ,  H03L7/00

CPC分类号： H03K19/00315

摘要： A powerup sequencing circuit and method generates an artificial supply voltage until the actual supply voltage is at a suitable level. An artificial supply source, such as a pull up circuit, is coupled to a node that receives a first supply voltage, such as an I/O buffer voltage. The pull up circuit is also coupled to an isolatable source voltage node. The isolatable source voltage node is the node that causes the actual second supply voltage. A temporary isolation circuit is operatively coupled to the pull up circuit and is operatively interposed between the node that receives the first supply voltage and the isolatable source voltage node. The pull up circuit provides a temporary or artificial second supply voltage level to an on chip circuit, such as an I/O buffer circuit or other suitable circuit that may, for example, be multi-voltage supply dependent. The temporary supply voltage is provided to the on chip circuit during powerup and the temporary isolation circuit operatively isolates the isolatable source voltage node until the second supply voltage reaches a suitable level and turns off the temporary isolation circuit.

摘要翻译： 上电顺序电路和方法产生人造电源电压，直到实际电源电压处于适当的电平。 诸如上拉电路的人造供电源耦合到接收诸如I / O缓冲器电压的第一电源电压的节点。 上拉电路还耦合到可隔离的源极电压节点。 可分离源电压节点是导致实际第二电源电压的节点。 临时隔离电路可操作地耦合到上拉电路，并且可操作地插入在接收第一电源电压的节点和可隔离源电压节点之间。 上拉电路为片上电路（例如I / O缓冲电路或其他合适的电路提供暂时或人造的第二电源电压），例如可能是多电压电源。 在上电期间临时供电电压被提供给片上电路，并且临时隔离电路可操作地隔离可隔离源电压节点，直到第二电源电压达到适当的电平并关断临时隔离电路。

公开(公告)号：US09347836B2

公开(公告)日：2016-05-24

申请号：US13296804

申请日：2011-11-15

申请人： Grigori Temkine ,  Filipp Chekmazov ,  Paul Edelshteyn ,  Oleg Drapkin ,  Kristina Au

发明人： Grigori Temkine ,  Filipp Chekmazov ,  Paul Edelshteyn ,  Oleg Drapkin ,  Kristina Au

IPC分类号： G01K7/01 ,  G06F1/20

CPC分类号： G01K7/01 ,  G06F1/206

摘要： A system and method for measuring integrated circuit (IC) temperature. An integrated circuit (IC) includes a thermal sensor and data processing circuitry. The thermal sensor utilizes switched currents provided to a reference diode and a thermal diode. The ratios of the currents provided to each of these diodes may be chosen to provide a given delta value between the resulting sampled diode voltages. At a later time, a different ratio of currents may be provided to each of these diodes to provide a second given delta value between the resulting sampled diode voltages. A differential amplifier within the data processing circuitry may receive the analog sampled voltages and determine the delta values. Other components within the data processing circuitry may at least digitize and store one or both of the delta values. A difference between the digitized delta values may calculated and used to determine an IC temperature digitized code.

摘要翻译： 一种用于测量集成电路（IC）温度的系统和方法。 集成电路（IC）包括热传感器和数据处理电路。 热传感器利用提供给参考二极管和热二极管的开关电流。 可以选择提供给这些二极管中的每一个的电流的比率以在所得到的采样二极管电压之间提供给定的Δ值。 在稍后的时间，可以向这些二极管中的每一个提供不同的电流比，以在得到的采样的二极管电压之间提供第二给定的Δ值。 数据处理电路内的差分放大器可以接收模拟采样电压并确定增量值。 数据处理电路内的其他组件可以至少数字化并存储增量值中的一个或两个。 可以计算数字化增量值之间的差异，并用于确定IC温度数字化代码。

公开(公告)号：US08238067B2

公开(公告)日：2012-08-07

申请号：US12332651

申请日：2008-12-11

申请人： Oleg Drapkin ,  Grigori Temkin ,  Peter Bade

发明人： Oleg Drapkin ,  Grigori Temkin ,  Peter Bade

IPC分类号： H02H9/00

CPC分类号： H02H9/046 ,  H01L27/0285

摘要： A method and integrated circuit renders a shunt structure non-conductive during a power up event or noise event for and in addition, during an electrostatic discharge event, keeps the shunt structure conductive for a period of time to discharge electrostatic energy through the shunt structure. In one example, a shunt structure, such as a transistor, is interposed between a power node and a ground node. Circuitry is operative during a power up event or noise event, to render the shunt structure non-conductive for a period of time during the power up event or during the noise event (when power is applied). Second circuit is operative, during an electrostatic discharge event, to keep the shunt structure conductive for a period of time to discharge electrostatic energy through the shunt structure. In one example, a plurality of resistor/capacitors (RC) circuits are utilized wherein the RC circuits have different time constants. In addition, an ESD feedback circuit is employed in conjunction with control logic to suitably control the ESD control logic during an ESD event. Circuitry is also used during a power up event to render the shunt structure non-conductive.

摘要翻译： 一种方法和集成电路在上电事件或噪声事件期间使分流结构不导电并且另外在静电放电事件期间保持分流结构导通一段时间以通过分流结构释放静电能量。 在一个示例中，诸如晶体管的分流结构被插入在功率节点和接地节点之间。 在上电事件或噪声事件期间，电路可操作，以在上电事件期间或在噪声事件期间（施加电力时）使分流结构不导通一段时间。 第二电路在静电放电事件期间操作，以使分流结构保持导电一段时间以通过分流结构释放静电能。 在一个示例中，使用多个电阻/电容器（RC）电路，其中RC电路具有不同的时间常数。 此外，ESD反馈电路与控制逻辑结合使用以在ESD事件期间适当地控制ESD控制逻辑。 在上电事件期间也使用电路来使分流结构不导电。

公开(公告)号：US20080284468A1

公开(公告)日：2008-11-20

申请号：US11749002

申请日：2007-05-15

申请人： Oleg Drapkin ,  Grigori Temkine ,  Marcus Ng ,  Kevin Yikai Liang ,  Arvind Bomdica ,  Siji Menokki Kandiyil ,  Ming So ,  Samu Suryanarayana

发明人： Oleg Drapkin ,  Grigori Temkine ,  Marcus Ng ,  Kevin Yikai Liang ,  Arvind Bomdica ,  Siji Menokki Kandiyil ,  Ming So ,  Samu Suryanarayana

IPC分类号： H03K19/0175

CPC分类号： H03K19/00384 ,  H03K17/223 ,  H04L25/028

摘要： An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.

摘要翻译： 集成电路能够通过使用功率斜坡控制的通信缓冲器逻辑来控制通信信号，以基于电压源上的检测到的电压来产生输出通信信号。 为电源斜坡控制的通信缓冲逻辑电源供电需要电压源。 可以使用功率斜坡传感器逻辑来检测电压源上的电压。 如果检测到的电压大于或等于预定电压电平，则输出通信信号基于核心逻辑输出信号。 如果检测到的电压小于预定电压电平，则将输出通信信号预定为三态输出通信信号，逻辑1输出通信信号和逻辑零输出通信信号之一。 功率斜坡控制通信缓冲器逻辑还可以响应于检测到的电压而基于输入通信信号生成核心逻辑输入信号。