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公开(公告)号：USD812802S1
公开(公告)日：2018-03-13
申请号：US29562202
申请日：2016-04-22
Applicant: Bradley Garrett , Travis Boyle , Alexander Ross , William Getzinger , John Leon
Designer： Bradley Garrett , Travis Boyle , Alexander Ross , William Getzinger , John Leon
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公开(公告)号：US09431275B2
公开(公告)日：2016-08-30
申请号：US13209898
申请日：2011-08-15
Applicant: Randy Bindrup , W. Eric Boyd , John Leon , James Yamaguchi , Angel Pepe
Inventor： Randy Bindrup , W. Eric Boyd , John Leon , James Yamaguchi , Angel Pepe
IPC: H01L23/488 , H01L21/56 , H01L23/00 , H01L25/10
CPC classification number: H01L24/45 , H01L21/568 , H01L23/498 , H01L23/49811 , H01L24/05 , H01L24/24 , H01L24/82 , H01L24/96 , H01L25/105 , H01L2224/04042 , H01L2224/45144 , H01L2224/45541 , H01L2224/82001 , H01L2224/96 , H01L2225/1035 , H01L2225/1041 , H01L2225/1052 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/18162 , H01L2924/19107 , H01L2924/3011 , H01L2224/82 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/48
Abstract: A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.
Abstract translation: 一种可堆叠的集成电路芯片层和模块装置，其避免了在包含集成电路管芯的层的外表面上使用导电元件，利用常规引线键合设备来提供由引线键合段限定的导电路径， 封装在灌封材料中，以便限定可从该层的至少下表面或第二表面接近的导电引线键合“通孔”。
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3.发明授权Method and system to centrally monitor the quality of images of financial documents 有权集中监控财务文件图像质量的方法和系统公开(公告)号：US08320635B2
公开(公告)日：2012-11-27
申请号：US11164722
申请日：2005-12-02
Applicant: Patrick S. McMonagle , Christine Collins , John Leon
Inventor： Patrick S. McMonagle , Christine Collins , John Leon
CPC classification number: G06K9/036 , G06K9/00979 , G06Q40/00 , G06Q40/02
Abstract: Method and system to centrally monitor the quality of images of financial documents. Embodiments of the present invention can provide a way to monitor and evaluate the quality of images of financial documents stored for remote access by financial institutions. In some embodiments, a standard quality analysis of at least some of the images is performed, and, based on the quality analysis, suspect images are identified to a responsible entity. For at least some of the images, a decisioning result from the responsible entity is recorded in association with information identifying the images. The quality analysis can be applied based on exclusion criteria such as an amount threshold, certain routing information, etc. The suspect images can be identified by sending a quality results file to the responsible entity, and a decisioning result can be received in a decisioning results file.
Abstract translation: 集中监控财务文件图像质量的方法和系统。 本发明的实施例可以提供一种监视和评估由金融机构远程访问存储的财务文件的图像质量的方法。 在一些实施例中，执行至少一些图像的标准质量分析，并且基于质量分析，可疑图像被识别为负责实体。 对于至少一些图像，与识别图像的信息相关联地记录来自负责实体的决定结果。 质量分析可以基于排除标准（如数量阈值，某些路由信息等）应用。可以通过向负责实体发送质量结果文件来识别可疑图像，并可以在决策结果中接收决策结果 文件。
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4.发明申请Field programmable gate array utilizing dedicated memory stacks in a vertical layer format 有权利用垂直层格式的专用存储器堆栈的现场可编程门阵列公开(公告)号：US20080074144A1
公开(公告)日：2008-03-27
申请号：US11897938
申请日：2007-08-31
Applicant: Volkan Ozguz , Randolph Carlson , Keith Gann , John Leon , W. Boyd
Inventor： Volkan Ozguz , Randolph Carlson , Keith Gann , John Leon , W. Boyd
IPC: H03K19/173
CPC classification number: H03K19/1776 , G01R31/318519 , G06F9/3802 , H03K19/177 , H03K19/17792
Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.
Abstract translation: 现场可编程门阵列，耦合到FPGA的接入引线网络和电耦合到接入引线网络的多个存储器。 FPGA，接入引线网络和多个存储器被布置和配置为以可变字宽度操作，即具有在1和最大位数之间的字宽度。 绝对最大字宽度可以与m.times.N一样大m其中m是每个存储器芯片的字宽度位数，N是存储器芯片的数量。
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公开(公告)号：US20050122758A1
公开(公告)日：2005-06-09
申请号：US11037490
申请日：2005-01-18
Applicant: Randolph Carlson , Volkan Ozguz , Keith Gann , John Leon
Inventor： Randolph Carlson , Volkan Ozguz , Keith Gann , John Leon
IPC: G01R31/3185 , G06F9/38 , H03K19/177 , G11C5/06
CPC classification number: G01R31/318519 , G06F9/3802 , H01L2224/16227 , H01L2924/15311 , H03K19/17736 , H03K19/1776 , H03K19/1778 , H03K19/17796
Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.
Abstract translation: 现场可编程门阵列，耦合到FPGA的接入引线网络和电耦合到接入引线网络的多个存储器。 FPGA，接入引线网络和多个存储器被布置和配置为以可变字宽度操作，即具有在1和最大位数之间的字宽度。 绝对最大字宽度可以与m.times.N一样大m其中m是每个存储器芯片的字宽度位数，N是存储器芯片的数量。
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Patent Agency Ranking
公开(公告)号：US6161296A
公开(公告)日：2000-12-19
申请号：US218797
申请日：1998-12-21
Applicant: John Leon Thomas Joseph Davio
Inventor： John Leon Thomas Joseph Davio
CPC classification number: B23K37/0426 , B23K2101/06 , Y10T29/53961 , Y10T29/53987
Abstract: An alignment device for use in welding which includes a saddle style support which rests upon a first pipe. A second pipe is clamped to the saddle style support in an orientation substantially perpendicular to the first pipe upon which the saddle style support rests. The second pipe serves as a carrier member of a fitting, such as a weldolet. Cinch straps can be used with the saddle style support to facilitate welding on the underside of horizontal pipes or on vertical pipes.
Abstract translation: 一种用于焊接的对准装置，其包括搁置在第一管上的马鞍式支架。 第二管子以基本上垂直于第一管道的方向被夹紧到鞍形支撑件上，鞍形支撑件搁置在该第一管道上。 第二管用作配件的承载构件，例如焊缝。 貂皮带可以与鞍座支撑一起使用，以便于在水平管道的下侧或垂直管道上进行焊接。
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公开(公告)号：US5850789A
公开(公告)日：1998-12-22
申请号：US898098
申请日：1997-07-22
Applicant: Andreas Johannes Rudolf , David Leo Fox , John Leon Fox , Richard Orton Toles , David Anthony Debski , William Webb Early , Christian Beers
Inventor： Andreas Johannes Rudolf , David Leo Fox , John Leon Fox , Richard Orton Toles , David Anthony Debski , William Webb Early , Christian Beers
CPC classification number: B41F27/005 , Y10S101/36
Abstract: An apparatus and method for mounting a plurality of plates onto a carrier sheet includes a table mounted on a stationary base, each plate having a first and a second registration mark thereon. A first camera assembly is moveably attached to a support adjacent the table and is connected to a first video monitor for viewing the first registration marks. A second video camera is moveably attached to the support adjacent the table and is connected to a second video monitor for viewing the second registration marks. Linear actuators are connected to the first and the second camera assemblies and to the table for independently moving each camera assembly relative to the table. A motion controller is connected to the linear actuators for sending moving signals thereto, and generates at least two moving signals corresponding to the two registration marks for each plate. Each plate is positioned on the carrier sheet beneath the first and the second camera assemblies so that the first registration mark aligns with a cross-hair image on the first video monitor and the second registration mark aligns with a cross-hair image on the second video monitor.
Abstract translation: 用于将多个板安装在载体片上的装置和方法包括安装在固定基座上的工作台，每个板上具有第一和第二对准标记。 第一相机组件可移动地附接到邻近桌子的支撑件，并且连接到第一视频监视器以观看第一对准标记。 第二摄像机可移动地附接到邻近桌子的支撑件，并连接到第二视频监视器以观看第二对准标记。 线性致动器连接到第一和第二相机组件和桌子，用于相对于桌子独立地移动每个相机组件。 运动控制器连接到用于向其发送运动信号的线性致动器，并且产生对应于每个板的两个对准标记的至少两个运动信号。 每个板被定位在第一和第二相机组件下面的载体片上，使得第一对准标记与第一视频监视器上的十字头图像对准，并且第二对准标记与第二视频上的十字头图像对准 监控。
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8.发明授权Field programmable gate array utilizing dedicated memory stacks in a vertical layer format 有权利用垂直层格式的专用存储器堆栈的现场可编程门阵列公开(公告)号：US07902879B2
公开(公告)日：2011-03-08
申请号：US12639625
申请日：2009-12-16
Applicant: Volkan H. Ozguz , Randolph S. Carlson , Keith D. Gann , John Leon , W. Eric Boyd
Inventor： Volkan H. Ozguz , Randolph S. Carlson , Keith D. Gann , John Leon , W. Eric Boyd
CPC classification number: H03K19/1776 , G01R31/318519 , G06F9/3802 , H03K19/177 , H03K19/17792
Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m*N where m is the number of word width bits per memory chip and N is the number of memory chips.
Abstract translation: 现场可编程门阵列，耦合到FPGA的接入引线网络和电耦合到接入引线网络的多个存储器。 FPGA，接入引线网络和多个存储器被布置和配置为以可变字宽度操作，即具有在1和最大位数之间的字宽度。 绝对最大字宽度可以与m * N一样大，其中m是每个存储器芯片的字宽度位数，N是存储器芯片的数量。
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9.发明授权Field programmable gate array utilizing dedicated memory stacks in a vertical layer format 有权利用垂直层格式的专用存储器堆栈的现场可编程门阵列公开(公告)号：US07649386B2
公开(公告)日：2010-01-19
申请号：US11897938
申请日：2007-08-31
Applicant: Volkan H. Ozguz , Randolph S. Carlson , Keith D. Gann , John Leon , W. Eric Boyd
Inventor： Volkan H. Ozguz , Randolph S. Carlson , Keith D. Gann , John Leon , W. Eric Boyd
CPC classification number: H03K19/1776 , G01R31/318519 , G06F9/3802 , H03K19/177 , H03K19/17792
Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.
Abstract translation: 现场可编程门阵列，耦合到FPGA的接入引线网络和电耦合到接入引线网络的多个存储器。 FPGA，接入引线网络和多个存储器被布置和配置为以可变字宽度操作，即具有在1和最大位数之间的字宽度。 绝对最大字宽度可以与m.times.N一样大m其中m是每个存储器芯片的字宽度位数，N是存储器芯片的数量。
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公开(公告)号：US07241579B2
公开(公告)日：2007-07-10
申请号：US10451007
申请日：2001-12-18
Applicant: John Leon Andrews , Celia Patricia Briscoe , Diane Michele Ignar , Allison Isobel Muir , Howard Ray Sauls, Jr. , Mohammad Tadayyon
Inventor： John Leon Andrews , Celia Patricia Briscoe , Diane Michele Ignar , Allison Isobel Muir , Howard Ray Sauls, Jr. , Mohammad Tadayyon
IPC: G01N33/53 , G01N33/58 , G01N33/566
CPC classification number: G01N33/92 , C12Q1/6897
Abstract: Methods of screening for ligands of the GPR40 receptor are provided, including methods utilizing fatty acid GPR40 ligands.
Abstract translation: 提供了筛选GPR40受体配体的方法，包括利用脂肪酸GPR40配体的方法。
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