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    Three-dimensional module comprised of layers containing IC chips with overlying interconnect layers
    1.
    发明授权
    Three-dimensional module comprised of layers containing IC chips with overlying interconnect layers 有权
    由包含具有上覆互连层的IC芯片的层组成的三维模块

    公开(公告)号：US07239012B2

    公开(公告)日：2007-07-03

    申请号：US10951990

    申请日：2004-09-28

    Applicant: Angel Pepe ,  James Yamaguchi

    Inventor： Angel Pepe ,  James Yamaguchi

    IPC: H01L23/02 ,  H01L23/58 ,  H01L23/48

    CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L22/32 ,  H01L23/3121 ,  H01L23/5388 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2924/1433 ,  H01L2924/18161

    Abstract: A pre-formed integrated circuit chip-containing module formed from layers is disclosed. Each layer contains an integrated circuit chip that is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip. A plurality of interconnect assemblies and chips are bonded together to form a corresponding plurality of electronic packages. Each layer is bonded to form a stack of integrated circuit containing layers.

    Abstract translation: 公开了一种由层形成的预先形成的集成电路芯片的模块。 每个层包含通过与预先形成的集成电路芯片分开形成互连组件而封装在电子封装中的集成电路芯片。 如果互连组件测试良好，则它连接到准备好的集成电路芯片。 互连组件被翻转接合到芯片。 互连组件和芯片被钝化或封装成整体结构以提供电子封装。 在互连层中限定至少一个测试焊盘，该测试焊盘可以被访问并电连接在测试焊盘的相对侧上。 芯片底部填充有绝缘材料，以去除芯片和互连组件之间的所有空隙。 然后将集成电路芯片变薄。 访问测试板来测试芯片。 多个互连组件和芯片结合在一起以形成相应的多个电子封装。 每个层被结合以形成包含层的集成电路的堆叠。

    Three-dimensional module comprised of layers containing IC chips with overlying interconnect layers and a method of making the same
    4.
    发明申请
    Three-dimensional module comprised of layers containing IC chips with overlying interconnect layers and a method of making the same 有权
    由包含具有上覆互连层的IC芯片的层构成的三维模块及其制造方法

    公开(公告)号：US20050037540A1

    公开(公告)日：2005-02-17

    申请号：US10951990

    申请日：2004-09-28

    Applicant: Angel Pepe ,  James Yamaguchi

    Inventor： Angel Pepe ,  James Yamaguchi

    IPC: H01L21/68 ,  H01L23/31 ,  H01L23/538 ,  H01L23/58 ,  H01L21/44 ,  H01L21/48

    CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L22/32 ,  H01L23/3121 ,  H01L23/5388 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2924/1433 ,  H01L2924/18161

    Abstract: A pre-formed integrated circuit chip is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip. A plurality of interconnect assemblies and chips are bonded together to form a corresponding plurality of electronic packages.

    Abstract translation: 通过与预先形成的集成电路芯片分开形成互连组件，预先形成的集成电路芯片被封装到电子封装中。 如果互连组件测试良好，则它连接到准备好的集成电路芯片。 互连组件被翻转接合到芯片。 互连组件和芯片被钝化或封装成整体结构以提供电子封装。 在互连层中限定至少一个测试焊盘，该测试焊盘可以被访问并电连接在测试焊盘的相对侧上。 芯片底部填充有绝缘材料，以去除芯片和互连组件之间的所有空隙。 然后将集成电路芯片变薄。 访问测试板来测试芯片。 多个互连组件和芯片结合在一起以形成相应的多个电子封装。

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