公开(公告)号：US20100291735A1

公开(公告)日：2010-11-18

申请号：US12844555

申请日：2010-07-27

Applicant: Volkan Ozguz ,  Angel Pepe ,  James Yamaguchi ,  W. Eric Boyd ,  Douglas Albert ,  Andrew Camien

Inventor： Volkan Ozguz ,  Angel Pepe ,  James Yamaguchi ,  W. Eric Boyd ,  Douglas Albert ,  Andrew Camien

IPC: H01L21/70 ,  H01L21/60

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Abstract translation: 公开了一种可堆叠层和堆叠多层模块。 单个集成电路裸片在晶片级进行测试和处理，以创建用于将电信号从芯片的有源表面路由到非活动表面的垂直区域互连通孔。 使用一系列半导体处理步骤，在掩模版级上在晶片上的每个管芯上的预定位置处形成通孔。 晶片被钝化，并且通孔填充有导电材料。 裸片上的接合焊盘被暴露，并且应用来自用户选择的接合焊盘和通孔的金属化重新路由。 然后将晶片分段以形成薄的可堆叠层，其可以使用导电通孔堆叠并垂直电互连，形成高密度电子模块，其可以进一步堆叠并互连以形成更大的更复杂的堆叠。

公开(公告)号：US20090078649A1

公开(公告)日：2009-03-26

申请号：US11858380

申请日：2007-09-20

Applicant: INDJE OGNIANOV MIHAYLOV ,  Douglas Albert Hope

Inventor： INDJE OGNIANOV MIHAYLOV ,  Douglas Albert Hope

IPC: B01D15/08 ,  B01D15/04

CPC classification number: C02F1/42 ,  B01J39/04 ,  B01J49/06 ,  B01J49/53 ,  C02F2101/20 ,  C02F2303/16

Abstract: A method for selective removal of cadmium from a feed solution also containing other metals such as nickel (Ni) and/or cobalt (Co), utilizing a thiourea based ion exchange resin, and a method for eluting cadmium adsorbed on the thiourea based resin.

Abstract translation: 还可以使用硫脲类离子交换树脂从含有镍（Ni）和/或钴（Co）等其他金属的原料溶液中选择性除去镉的方法以及硫脲类树脂上吸附的镉的洗脱方法。

公开(公告)号：US20050077621A1

公开(公告)日：2005-04-14

申请号：US10968572

申请日：2004-10-19

Applicant: Keith Gann ,  Douglas Albert

Inventor： Keith Gann ,  Douglas Albert

IPC: H01L21/98 ,  H01L25/10 ,  H01L23/495

CPC classification number: H01L25/50 ,  H01L23/49575 ,  H01L24/48 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2225/06551 ,  H01L2225/1011 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  Y10T29/49121 ,  Y10T29/49146 ,  Y10T29/49171 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metalizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metalizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metalizations, which are disposed in part on the bare insulative surface.

Abstract translation: 这样的存储芯片的预包装芯片被垂直堆叠并且将其端子对准地结合在一起。 外部引线框架被移除，包括延伸到包装中的部分。 接合线现在暴露在堆叠的集体侧表面上。 在没有接合线与引线框架连接的区域，留下裸露的绝缘表面。 接触层设置在堆叠的顶部，并且垂直金属化被限定在堆叠上，以将导线的端部连接到接触层，并且因此接触接触层顶表面上的焊盘。 垂直金属化被布置和配置为连接芯片的所有共同的共享端子，而每个芯片的控制和数据输入/输出信号分别连接到部分地设置在裸绝缘表面上的金属化。

公开(公告)号：US06377833B1

公开(公告)日：2002-04-23

申请号：US09390048

申请日：1999-09-03

Applicant: Douglas Albert

Inventor： Douglas Albert

IPC: A61B505

CPC classification number: A61B5/0484 ,  A61B5/055 ,  G01R33/4806 ,  G06F19/00

Abstract: A system calibrates a user's brain region (e.g., the primary visual cortex or V1 region) to actual sensory information (e.g., the visual field), and enables imagined sensory information (e.g.; dynamic mental imagery) to be interpreted as computer input. The system includes a configuration engine and an input device control engine. The configuration engine includes a test pattern; a functional information gatherer for presenting the test pattern to a user; a brain-scanning device interface for obtaining functional information from a region in the user's brain that provides a physiological response to the test pattern and that receives feedback corresponding to imagined sensory information; and a mapping engine for using the functional information to map the user's brain region to the test pattern. The input device control engine includes a brain-scanning device interface for obtaining functional information from a brain region that provides a physiological response to actual sensory information and that receives feedback corresponding to imagined sensory information; an interpretation engine for interpreting the feedback; and a computer control engine for using the interpreted feedback as computer input.

Abstract translation: 系统将用户的大脑区域（例如，主要视觉皮层或V1区域）校准为实际的感觉信息（例如，视野），并且使想象的感觉信息（例如，动态心理图像）被解释为计算机输入。 该系统包括配置引擎和输入设备控制引擎。 配置引擎包括测试模式; 用于向用户呈现测试模式的功能信息采集器; 脑扫描设备接口，用于从用户的大脑中的区域获得功能信息，该功能信息为测试模式提供生理响应并且接收与想象的感觉信息相对应的反馈; 以及用于使用功能信息将用户的大脑区域映射到测试图案的映射引擎。 所述输入装置控制引擎包括脑扫描装置接口，用于从脑区获得功能信息，所述功能信息对实际的感觉信息提供生理反应，并接收对应于想象的感觉信息的反馈; 用于解释反馈的解释引擎; 以及用于将解释的反馈用作计算机输入的计算机控制引擎。

公开(公告)号：US20140156561A1

公开(公告)日：2014-06-05

申请号：US14004491

申请日：2012-03-15

Applicant: Ressa Gayle Steele ,  Douglas Albert Ross ,  Garry Allen Brimson

Inventor： Ressa Gayle Steele ,  Douglas Albert Ross ,  Garry Allen Brimson

IPC: B65D1/36 ,  G06Q90/00

CPC classification number: B65D1/36 ,  B65D2203/10 ,  G06Q90/00

Abstract: A method for allowing security personnel in screening stations to more quickly identify prohibited articles and to identify and interrogate the screened individual responsible for the prohibited article, thereby improving throughput and reducing human error. If an operator observes articles which raise a security concern, the operator isolates the location of such articles by referencing the compartment in the tray where it is located and optionally whether the article is in a high or low position in the compartment and by referencing a tray's unique identifier. A security tray design is provided to carry out the method which includes discrete delineated compartments, and optionally a unique identifier and an area for displaying the screened individual's identification to connect the individual to a unique tray, to assist in preventing individuals from gaining access to restricted areas with prohibited articles.

Abstract translation: 一种允许安检人员在检查站中更快速地识别被禁物品的方法，并且识别和询问对被禁物品负责的被筛选人员，从而提高吞吐量并减少人为错误。 如果操作者观察到引起安全问题的物品，则操作者通过参考位于其中的托盘中的隔室并且可选地，物品是否处于隔间中的高或低位置并通过参考托盘的 唯一标识符。 提供安全托盘设计以执行包括离散描绘隔间的方法，以及可选地唯一的标识符和用于显示被筛选的个人标识以将个人连接到唯一的托盘的区域，以帮助防止个人获得限制 禁止物品的区域

公开(公告)号：US07998441B2

公开(公告)日：2011-08-16

申请号：US11858380

申请日：2007-09-20

Applicant: Indje Ognianov Mihaylov ,  Douglas Albert Hope

Inventor： Indje Ognianov Mihaylov ,  Douglas Albert Hope

IPC: B01J45/00

CPC classification number: C02F1/42 ,  B01J39/04 ,  B01J49/06 ,  B01J49/53 ,  C02F2101/20 ,  C02F2303/16

Abstract: A method for selective removal of cadmium from a feed solution also containing other metals such as nickel (Ni) and/or cobalt (Co), utilizing a thiourea based ion exchange resin, and a method for eluting cadmium adsorbed on the thiourea based resin.

Abstract translation: 还可以使用硫脲类离子交换树脂，从含有镍（Ni）和/或钴（Co）等其他金属的原料溶液中选择性除去镉的方法以及硫脲类树脂上吸附的镉的洗脱方法。

公开(公告)号：US06983441B2

公开(公告)日：2006-01-03

申请号：US10183902

申请日：2002-06-28

Applicant: Douglas Albert Wescott

Inventor： Douglas Albert Wescott

IPC: H03K19/00 ,  G06F17/50 ,  G01R31/28

CPC classification number: G11C29/48 ,  G11C2029/0401 ,  G11C2029/3202

Abstract: A method for embedding a Joint Test Action Group (JTAG) standard IEEE 1149.1 host controller into a field programmable gate array (FPGA) for platform development and DSP programming, and boundary scan of targeted hardware using JTAG commands and architecture is described. The FPGA-based JTAG host controller is bussed directly into the FPGA core, bypassing the board's JTAG communication port.

Abstract translation: 描述了一种将联合测试动作组（JTAG）标准IEEE 1149.1主机控制器嵌入到用于平台开发和DSP编程的现场可编程门阵列（FPGA）以及使用JTAG命令和架构的目标硬件的边界扫描的方法。 基于FPGA的JTAG主机控制器直接放入FPGA内核，绕过了该板的JTAG通信端口。

公开(公告)号：US20050277288A1

公开(公告)日：2005-12-15

申请号：US11150712

申请日：2005-06-10

Applicant: Volkan Ozguz ,  Angel Pepe ,  James Yamaguchi ,  W. Boyd ,  Douglas Albert ,  Andrew Camien

Inventor： Volkan Ozguz ,  Angel Pepe ,  James Yamaguchi ,  W. Boyd ,  Douglas Albert ,  Andrew Camien

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/48 ,  H01L21/50 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Abstract translation: 公开了一种可堆叠层和堆叠多层模块。 单个集成电路裸片在晶片级进行测试和处理，以创建用于将电信号从芯片的有源表面路由到非活动表面的垂直区域互连通孔。 使用一系列半导体处理步骤，在掩模版级上在晶片上的每个管芯上的预定位置处形成通孔。 晶片被钝化，并且通孔填充有导电材料。 裸片上的接合焊盘被暴露，并且应用来自用户选择的接合焊盘和通孔的金属化重新路由。 然后将晶片分段以形成薄的可堆叠层，其可以使用导电通孔堆叠并垂直电互连，形成高密度电子模块，其可以进一步堆叠并互连以形成更大的更复杂的堆叠。

公开(公告)号：US20050121227A1

公开(公告)日：2005-06-09

申请号：US10726888

申请日：2003-12-04

Applicant: Douglas Albert

Inventor： Douglas Albert

IPC: H01L21/60 ,  H05K3/32 ,  H05K3/36 ,  H05K1/18 ,  H05K3/34

CPC classification number: H05K3/328 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/30107 ,  H05K3/366 ,  H05K2201/10234 ,  H05K2201/10727 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49142 ,  Y10T29/49144 ,  H01L2224/05599

Abstract: A method for electrical interconnection of angularly disposed and abutted conductive patterns is disclosed along with a device created from the method. Conventional wire bonding equipment is used to apply a conductive metal ball at the junction of angularly disposed conductive patterns by orienting a cornerbond assembly whereby one or more conductive metal balls are orthogonally applied and electrically connected to the respective conductive patterns.

Abstract translation: 公开了一种用于角配置和邻接的导电图案的电互连的方法以及从该方法创建的装置。 常规的引线接合设备用于通过定向拐角组合件来将角度设置的导电图案的接合处施加导电金属球，由此一个或多个导电金属球正交地施加并电连接到相应的导电图案。

公开(公告)号：US3538882A

公开(公告)日：1970-11-10

申请号：US3538882D

申请日：1969-06-25

Applicant: DOUGLAS ALBERT JOHN PRICE

Inventor： PRICE DOUGLAS ALBERT JOHN

IPC: G09F7/00 ,  G09F9/00

CPC classification number: G09F7/00 ,  Y10S40/907